Cray Research, Inc.

Richard R Steitz

Melvin C August

Eugene F Neumann

Stephen E Nelson

Diane M Christie

James N Kruchowski

Delvin D Eberlein

Arthur Joseph Hebert

Paul E Schroeder

David L Duxstad

Peter J Wehner

Deanna M Dowdle

Paul M Knudsen

David F Leonard

Dean B Dudley

A method for simultaneously manufacturing metallized carriers from wafer-shaped substrates is described, wherein such wafer-shaped substrates permit the use of standard IC fabrication apparatus and methods. As a result, very thin and finely dimensioned traces can be deposited. Thin-film manufacturing techniques are used to create the high-density traces on the surface of the chip carriers, thereby permitting direct connections from the IC to the periphery of the carrier without the need for vias. A lid hermetically seals and protects the package. The traces are comprised of a plurality of metals to facilitate bonding, each of the metals homogeneous for a portion of the trace. One metal portion of the trace is of a type compatible with an IC chip placed in the carrier. Another metal portion of the trace is of a type compatible with a trace on a printed circuit board. A metal barrier is interposed between the metals to prevent metal diffusion from one metal to an adjoining portion of another metal.

Method of fabricating metallized chip carries from wafer-shaped

A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by 'opening' the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.

Integrated circuit chip carrier lid

A hermetically sealed carrier for integrated circuits has an IC placed on a carrier substrate, and an electrical lead apparatus, comprised of a highly heat resistant substrate with a metallized interconnect pattern deposited thereon, connected to the IC and brought out across and over the edges of the carrier substrate to facilitate electrical connection to a circuit board. A lid is provided which is placed over the IC. A low-melting temperature adhesive means is then placed on the lid-to-carrier interface and is exposed to heat hermetically sealing the IC. A hermetically sealed carrier including a single silicon die which includes both an active region where an integrated circuit may be fabricated and an inactive region is also provided. Electrical leads are electrically interconnected to the IC of the active region and extend to the periphery of the inactive region of the silicon die. A lid and adhesive means is provided for hermetically sealing the IC of the active region.

Non-metallized chip carrier

Method of fabricating metallized chip carriers from wafer-shaped

A ceramic chip carrier package for integrated circuits is described which provides reduced interlead capacitance. A cavity for the placement of the integrated circuit chip is centrally located on a substrate. The leads of the package are bridged between the cavity and the outer periphery of the substrate. The leads are bonded to the substrate using adhesive glass placed on the substrate at the outer periphery of the cavity and at the outer periphery of the substrate. Sealing glass is placed on the outer periphery of the substrate over the leads to provide a bonding material for a lid to the package. The area between the cavity and the outer periphery of the substrate has no adhesive or sealing glass which thus provides an air dielectric between the leads so that interlead capacitance is reduced. In a second preferred embodiment, a channel is provided in the ceramic substrate between the periphery of the cavity and the periphery of the substrate to control the flow of adhesive glass and sealing glass so that the glasses do not migrate onto the leads. Since the air dielectric constant is lower than the glass dielectric constant, the interlead capacitance is lower than that found in prior art packages.

Reduced capacitance chip carrier

A flexible automated bonding apparatus electrically interconnects integrated circuit carriers, printed circuit boards, and other devices. A metallized interconnect pattern is deposited on the surface of the substrate. The metallized interconnects in the pattern span apertures created in the substrate using an excimer laser. Thus, the metallized interconnects can be electrically bonded through the apertures to elements lying underneath the substrate.

Flexible automated bonding method and apparatus

A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by 'operating' the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.

Chip carrier with terminating resistive elements

Method of making a chip carrier with terminating resistive elements

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Chippewa Falls, WI, United States of America

Richard R Steitz