International Business Machines Corporation

Richard R Guyette

Robert J Dugan

Roger L Cormier

Paul J Brown

Carl Zeitler, Jr

Paul J Wanish

Ming C Hao

Casper A Scalzi

Allan Samuel Meritt

Glenn W Sears, Jr

Arthur L Levin

George A McClain

David H Wansor

Eddie T Hall

David L Strong

Ronald L Hankison

Stephen R Newson

The disclosure provides a unique multiprocessing (MP) method for executing on plural CPUs of the MP a uniprocessor system (UPS) program not written to run on a MP system. Separate copies of the UPS are provided in the shared main storage (MS) of the MP. A hypervisor type of control program (called a partitioned multiprocessing system, PMP) uses the MP method to enable simultaneous execution of the plural copies of a UPS on different CPUs of the MP as UPS guest virtual machines. PMP can dedicate any CPU to the sole execution of a particular copy of UPS. The copies of the UPS run on the different CPUs independently of each other, but they may share I/O devices.

Partitioned multiprocessor programming system

A channel for a data processing system is provided with a time of day clock that is synchronized with the time of day clock of the associated central processor. Both the central processor and the channel processor record times of particular events, and the channel uses these times to calculate two times called Function Pending and Function Active. Both times begin when the central processor executes an instruction to begin an I/O operation. Function Pending ends when the channel has made successful initial selection. This time shows delays by the channel processor in scheduling the channel control unit, and device resources for I/O operations. Function Active ends at Channel End. A new instruction, Set Channel Monitor, enables or disables these measurements. An information block for each subchannel defines one of several measurement modes for a subchannel or disables the subchannel from measurement.

Method and apparatus for measurements of channel operation

Multiprocessing systems having changeable CPU configurations generate unique changeable identifications (ID's). These are presented by I/O channels over various I/O connection paths, in association with special path defining commands and function data. Related path state indications are stored peripherally in path map tables and define path group associations for sustaining path-independent I/O operations. When a device is reserved via one path in a path group the reserve affiliation is extended automatically (in the path tables ) to each path in the group, thereby rendering each path accessible in a reserved mode. The path defining commands are used for adding paths to, resigning paths from and disbanding groups. Special sensing commands are used for sensing path reservation and grouping states. When a command for adding or resigning a path is presented to a reserved device via one path in a group the reserve is automatically realigned to the enlarged or reduced group. When a command for disbanding a group is presented to a reserved device the reserve is realigned to apply only to the path on which the command is presented. The foregoing special commands are required to be obeyed by the device even if it currently has a conflicting allegiance to the same system or another system. Consequently, paths can be added to an established path group without requiring potentially premature release of any allegiance.

Method for establishing variable path group associations and

A new instruction called Test Subchannel assures that one processor will not begin an I/O operation with device status information that has been outdated by an operation of another processor. When a device has status to present, a status pending bit and an interruption pending bit are set in the channel subsystem and an interruption request is made. When a processor accepts an interruption, the channel system resets the interruption pending bit but not the status pending bit. The processor that accepts the interruption updates the unit control block (UCB) in main store and resets the status pending bit in the subchannel unless the UCB has been locked by another processor that is starting an I/O operation on the same device. This invention prevents the other processor from operating with outdated status information in the UCB. A processor that has locked the UCB uses Test Subchannel to test the Status Pending bit in the subchannel. If status is pending, the processor executes a routine to update the UCB. Optionally, when a processor that is handling an interruption finds the UCB locked, it sets a flag bit in the UCB lock word. Before a processor resets the UCB lock, it checks the lock word and executes the Test Subchannel instruction if the flag is set.

Independent handling of I/O interrupt requests and associated status

Apparatus is provided to permit a processor to interrupt computer input/output operations and later resume the same operations. The apparatus disconnects the input/output device involved in the operations from the channel to free the channel for other operations during the suspension.

Host control of suspension and resumption of channel program execution

Program instruction TPI (Test Pending Interruption) and associated data processor sequence controls for its execution enable interruption handling programs to operate in a shortened recursive mode relative to interruptions pending while such programs are in control of a data processor system. Execution of a TPI instruction sets a condition code distinguishing between pendency and non-pendency of a request for interruption in one associated class of interruptions. If an interruption request in that class is pending, the instruction execution controls clear (terminate) it. If more than one request is pending, a selected one is cleared. The selection is based on a predetermined priority ordering. Interruption code information is stored by the execution controls, indicating the source of the cleared request. The interruption handling program branches on the condition code and the interruption code information, to attend to the interruption task associated with the cleared request. Since that program is in control of the system when the TPI instruction is executed, the branch sequence may omit status saving operations and other operations associated with the handling of interruptions.

Program instruction mechanism for shortened recursive handling of

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Hopewell Junction, NY, United States of America

Richard R Guyette