Koninklijke Philips Corporation N.v.

U.S. Philips Corporation

Nxp B.v.

Richard Petrus Kleihorst

Renatus Josephus Van Der Vleuten

Andre Krijn Nieuwland

Albert Van Der Werf

Wilhelmus H Bruls

Adrianus Johannes Maria Denissen

Anteneh Alemu Abbo

Marc Joseph Rita Op De Beeck

Christian Hentschel

Nico Frits Benschop

Om Prakash Gangwal

Leonardus Hendricus Maria Sevat

Fabrice Cabrera

The subject matter hereof relates to error detection. Various example embodiments for error defection are disclosed. In an example method of error detection in a Module UnderTest (MUT), a parity signal representing the parity of an MUT output is compared to a parity signal representing the parity of an errorless MUT output. In an example system, an Actual Parity Generator provides a parity signal representing the parity of on MUT output, a State Parity Generator provides a parity signal representing the parity of an errorless MUT output, and a comparator compares these two parity signals.

Digital system and a method for error detection thereof

A processing element () forming part of a parallel processing array such as SIMD comprises an arithmetic logic unit (ALU) (), a multiplexer (MUX) (), an accumulator (ACCU) () and a flag register (FLAG) (). The ALU is configured to operate on a common instruction received by all processing elements in the processing array. The processing element () further comprises a storage element (SE) (), which supports the processing of local customized (i.e. data dependent) processing in the processing element (), such as lookup table operations and the storing local coefficient data.

Parallel processing array

The invention relates to a device for parallel data processing, a DSP. The device according to the invention comprises a processor matrix () in which processors () are arranged in rows () and columns (). Furthermore, the device () comprises first and second external data ports (). The rows () arranged in a stepwise manner and the columns are arranged in a stepwise manner. The processors () have a first processor data port (), which is connected with one of the first external data ports () by means of first essentially straight connection. The processors () further comprise a second processor data port (), which is connected with one of the second external data ports () by means of an essentially straight second connection (). The first connection () and the second connection () are oriented substantially orthogonal to each other. A problem associated with conventional DSPs is that the connections to and from the processors within the DSP take up large amounts of silicon area. By arranging both rows and columns of the DSP according to the invention in a stepwise manner the connections may be essentially straight, thus minimizing their lengths and thus the surface area occupied.

Device for parallel data processing as well as a camera system comprising such a device

The invention proposes a method of and a device for coding a signal (S) to obtain a scalable bit-stream (O). The signal (S) comprises blocks of values. Each block is represented () as a sequence of bit planes and the values are scanned and transmitted () in an order of decreasing bit plane significance. For each bit plane the scanning and transmitting () are performed in a rectangular scan zone (R/C) starting from a corner of the block (usually an upper-left corner). Preferably, the scanning and transmitting () is performed on each block individually. The produced bit-stream (O) is quantized to a desired bit-rate by simple truncating () the bit-stream (O) at a desired position.

Scalable coding

Storing of data items in a memory ( ) is provided wherein the data items are divided into successive data pieces of decreasing significance, and the data pieces are stored in respective parts of the memory ( ), and when applying a data piece to the memory ( ) in case all candidate memory parts are assigned to other data pieces: if the significance of the applied data piece is lower than a lowest significance of the other data pieces, discarding the applied data piece; if the significance of the applied data piece is higher than the lowest significance, storing the applied data piece in one of the candidate memory parts at expense of a given other data piece which has a lower significance than the significance of the applied data piece. Advantageous use of the invention is made in applications using a device of fixed storage capacity for storing compressible data, such as video, images, audio, speech.

Compressed storage of data items

Method and arrangement for encoding a video signal, wherein a selection ( ) is made between the generation of a motion-compensated encoded video signal (I, B, P) and the generation of a higher-resolution picture (I ). The creation of the higher-resolution picture (I ) relies on estimating motion in a series of subsequent pictures (f . . . ) of lower resolution. The higher-resolution picture (I ) is interpolated ( ) from these pictures (f . . . ). In a preferred embodiment of the invention, previously determined regions of interest (S(ROI)) are selected ( ) from the video signal. The pictures relating to these regions of interest (f . . . ) occupy less memory ( ) than entire pictures as picked up by an image sensor ( ). A conventional picture memory ( ) is sufficient to store the series of pictures (f . . . ) that relates to a certain region of interest. Motion estimation ( ) is performed on these pictures and their motion vectors (m) are stored in a vector memory ( ). The higher-resolution pictures (I ) are interpolated ( ) from the stored pictures (f . . . ) and their motion vectors (m). The invention is applicable for sensor ( )-encoder ( ) integration, for example in a camera system ( ).

Encoding a video signal

Disclosed is a method of compressing information for storage in a fixed size memory. The data items (D(k)) that constitute the information are divided into pieces (D(s,k)) of decreasing significance. For example, the DCT blocks of an image are hierarchically quantized ( ). The memory ( ) is organized in corresponding memory layers ( ). Successive memory layers have a decreasing number of memory locations. Every time a data item is applied to the memory, its less significant data pieces will have to compete with corresponding data pieces of previously stored data items. Depending on its contribution to perceptual image quality, the applied data piece is stored or the stored data piece is kept. Links ( ) are stored in the memory to identify the path along which a data item is stored. Eventually, the image is automatically compressed so as to exactly fit in the memory. FIG.

Compressed storage of information

A hybrid video encoder which carries out motion estimation and compensation ( ) in the transform domain. In such an encoder, the calculation of a prediction block (&Ycirc;) from previously encoded blocks (Z) stored in the transform-domain frame memory ( ) requires a large number of multiplications. This applies particularly to the motion estimation algorithm. In accordance with the invention, only a few DCT coefficients of candidate prediction blocks are calculated, for example, the DC coefficient and some AC coefficients. In a preferred embodiment, the AC coefficients are adaptively selected in dependence upon the motion vector which is being considered. The calculated coefficients of the candidate prediction blocks and the corresponding coefficients of the current input picture block (Y) are then compared to identify the best-matching prediction block.

Method and arrangement for video coding

A signal having blocks of values is coded by: producing respective bit-streams (DCT . . . DCT_N) for respective individual blocks, and obtaining a scalable bit-stream by cyclically and sequentially scanning selected parts (P P . . . ) of the respective bit-streams (DCT . . . DCT_N) of the respective individual blocks, wherein, in a given scanning cycle, the respective bit-streams (DCT . . . DCT_N) are scanned in an order of decreasing significance. In a further embodiment, the blocks represent a coded image and the given scanning cycle starts at a block approximately at a center of the coded image. In another embodiment, the blocks represent a coded image and the given scanning cycle scans the respective bit-streams in an image-adaptive order being determined by a predetermined criterion, such as a contrast value.

Scalable coding by scanning selected parts of respective bit-streams

A method and arrangement is disclosed for creating a high-resolution still picture. A sequence of lower-resolution pictures is subjected to motion-compensated predictive encoding, preferably by an MPEG encoder producing an IPPP. sequence of encoded pictures. The relatively small differences between successive pictures, which are due to motion of the image sensor or motion in the scene, become manifest in motion vectors with sub-pixel accuracy. The high-resolution picture is then created from the decoded pictures and the motion vectors generated by the encoder. The invention is particularly applicable in electronic still picture cameras with a storage medium. The MPEG encoder takes care of data compression, and the decoder also allows playback of the original moving video sequence.

Method and Arrangement for creating a high-resolution still picture

A system encodes an input video signal by subjecting the input video signal to noise reduction to obtain a noise-reduced signal, and encoding a difference between the noise-reduced signal and a prediction signal to produce an encoded signal. The system then decodes the encoded signal to obtain the prediction signal. In the system, the noise-reduction step comprises arithmetically combining the input video signal with the prediction signal.

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Eindhoven, Netherlands

Richard Petrus Kleihorst