Motorola Corporation

Richard Paul Wiley

Peter Redmond O'Brien

A data processing system which calculates timing delays in a circuit having a switching device (3). A computer processor (22) receives input describing a circuit and calculates the timing delays for each switching device (3) or stage. To perform each calculation the computer processor (22) models the circuit incorporating effective resistance R.sub.eff (24), Miller capacitance C.sub..mu. (7), and an associated Miller coefficient. The Miller coefficient is a defined by the behaviour of the model. The model is then reduced to a set of equations, the variables are determined, and the timing delay calculated. In one embodiment, successive stages are calculated to locate timing violations in circuit design. In alternate embodiments, models such as CRYSTAL (4) or the Sakurai model are enhanced by Miller capacitance considerations, however many other models may be used.

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Round Rock, TX, United States of America

Richard Paul Wiley