Intel Corporation

Richard Paul Mangold

Vinodh Gopal

Sanjeev N Trika

Keith L Shippy

Robert J Royer, Jr

Jawad Basit Khan

Knut Stener Grimsrud

Gary L Graunke

Anand S Ramalingam

Prashant S Damle

Paritosh Saxena

Nicholas D Triantafillou

Muthukumar Swaminathan

Paul J Thadikaran

Thomas J Hernandez

Raj K Ramanujan

Zion S Kwok

Ajit P Joshi

Richard L Maliszewski

Rajesh M Sankaran

Mark A Schmisseur

Murugasamy K Nachimuthu

Mahesh S Natu

David W Aucsmith

Richard L Coulson

Robert W Faber

James W Alexander

Theodros Yigzaw

Debra Hensgen

Daniel J Ragland

Kunal A Khochare

Jody L Pfotenhauer

Camille C Raad

Mark T Gross

Philip Hillier

Thomas R Bowen

Joseph M Nardone

Gerald S Holzhammer

Jason B Akers

Jeffrey W Ryden

Adam Greer Wright

David M Barth

Joerg Hartung

Reginald David Nepomuceno

Janet Yabeny Sholar

Shachi K Thakkar

Woojong Han

David A Lee

Curtis Edward Jutzi

Sudarshan Bala Cadambi

Karthikeyan Vaidyanathan

Brendan Traw

August A Camber

Sowmiya Jayachandran

Akshay Ramesh Kadam

Benjamin Graniello

Mark E Scott-Nash

Benjamin Walker

Simon Ramage

Andy M Rudoff

Jason A Gayman

Darren Lasko

Rowel S Garcia

Curtis A Gittens

Jason K Yu

Jonathan Bryan Stern

Akanksha Mehta

Shaun M Miller

Kevin Southern

Unnikrishnan Jayakumar

William B Lindquist

John A List

Rakan Maddah

Edward B Shin

Pranava Y Alekal

Christopher E Saleski

Douglas E Stewart

Chun L Yi

Technologies for media management for column-based memory systems include a memory controller including an indirection table. The memory controller receives a memory access to a column-addressable memory indicative of a memory row address. The memory controller determines a logical sub-block identifier based on the memory row address and looks up a physical sub-block identifier in the indirection table. The memory controller issues a redirected memory access indicative of the physical sub-block identifier to the column-addressable memory. The memory access may include a column read. The memory controller may perform a media management operation by copying or moving data from a source physical sub-block to a destination physical sub-block. The memory controller updates the indirection table with the destination physical sub-block for the associated logical sub-block identifier. Other embodiments are described and claimed.

Technologies for media management in column-addressable memory media systems

A write history buffer can prevent write disturb in memory, enabling a reduction in write disturb refresh rate and improvement in performance. A memory device can include circuitry to cause consecutive write commands to the same address to be spaced by an amount of time to reduce incidences of write disturb, and therefore reduce the required write disturb refresh rate and improve performance. In one example, a memory device receives multiple write commands to an address. In response to receipt of the multiple write commands, the first write command is sent to the memory and a timer is started. Subsequent write commands that are received after the first write command and before expiration of the timer are held in a buffer. After expiration of the timer, only the most recent of the subsequent write commands to the address is sent to the memory array. In this way, the subsequent write commands received during a time window after the first write command are coalesced and a single subsequent write command is sent to the memory.

Write disturb refresh rate reduction using write history buffer

Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices. In such an event, the volatile memory device is no longer contemporaneously accessed during read operations of the rank of active non-volatile memory devices.

Technologies for contemporaneous access of non-volatile and volatile memory in a memory device

One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.

Time tracking with patrol scrub

In one embodiment, an apparatus comprises a storage device to receive, from a computing host, a request to append data to a data log. The storage device is further to identify a memory location after a last segment of the data log, append the data to the data log by writing the data to the memory location after the last segment of the data log, and provide, to the computing host, a key comprising an identification of the memory location at which the data was appended to the data log.

Method and apparatus for improving performance of sequential logging in a storage device

Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.

Architectures and techniques for providing low-power storage mechanisms

A method is described. The method includes receiving an indication of an activity of load circuitry of a power supply. The method includes, in response to the indication, generating a first signal that describes the activity and a second signal that describes whether the event is initiating or completing. The method includes determining a weight amount from the first signal and adjusting a credit count by the weight amount up or down based on the second signal. The method includes comparing the credit count against a first threshold. The method includes calculating an average credit count that accounts for the credit count and previous credit counts and comparing the average credit count against a second threshold. The method includes adjusting an activity level of the load circuitry if either threshold is crossed.

Power management circuit with per activity weighting and multiple throttle down thresholds

Provided are an apparatus and method for using block windows configured in a memory module to provide block level access to memory chips in the memory module. A plurality of block windows are configured that map to addresses corresponding to the addressable locations in the memory chips. A read/write request is received indicating a requested read or write operation with respect to a target block window comprising one of the block windows. The requested read or write operation is performed with respect to the addresses that map to the target block window.

Apparatus and method to support a storage mode over a cache-line memory interface to a non-volatile memory dual in line memory module

Predictive memory maintenance in accordance with one aspect of the present description, can anticipate a failure of a selected primary memory die of an array, and pre-load a spare memory die with the data of the selected primary memory die deemed to have a likelihood of failure, prior to any actual failure of the selected memory die. In the event that the selected primary memory die does subsequently fail, the spare memory die pre-loaded with the data of the selected primary memory die can readily take the place of the failed primary memory die with a pre-existing copy of the data of the failed primary memory die. Other aspects are described herein.

Predictive memory maintenance

In response to a write operation on a storage element in a non-volatile memory device, a count provided by a global counter is stored to indicate a time at which the write operation occurs on the storage element. In response to receiving a request perform a read operation on the storage element, a determination is made of a demarcation voltage to apply for performing the read operation on the storage element, based on a progress of the global counter since the write operation on the storage element.

Determining demarcation voltage via timestamps

Systems and methods may provide for detecting that a read operation is directed to a memory region while the memory region is in a poisoned state and clearing the poisoned state if volatile data stored in the memory region does not correspond to a known data pattern. Additionally, the memory region may be maintained in the poisoned state if the volatile data stored in the memory region corresponds to the known data pattern. In one example, an error may be detected, wherein the error is associated with a write operation directed to the memory region. In such a case, the poisoned state may be set for the volatile data in response to the error and the known data pattern may be written to the memory region.

Clearing poison status on read accesses to volatile memory regions allocated in non-volatile memory

Methods and apparatus to accelerate boot time zeroing of memory based on Non-Volatile Memory (NVM) technology are described. In an embodiment, a storage device stores a boot version number corresponding to a portion of a non-volatile memory. A memory controller logic causes an update of the stored boot version number in response to each subsequent boot event. The memory controller logic returns a zero in response to a read operation directed at the portion of the non-volatile memory and a mismatch between the stored boot version number and a current boot version number. Other embodiments are also disclosed and claimed.

Accelerating boot time zeroing of memory based on non-volatile memory (NVM) technology

A mechanism is described for facilitating power governance of non-volatile memory devices using a power governing mechanism employed at a computing device according to one embodiment of the invention. A method of embodiments of the invention includes maintaining a credit pool having a plurality of credits to be released to a plurality of memory channels associated with a plurality of non-volatile memory devices. The plurality of credits may be used to provide sufficient power to perform memory operations associated with a computing device. The method may further include receiving a credit request having a petition to obtain one or more credits for a memory channel of the plurality of memory channels to facilitate performance of a memory operation, determining whether the one or more credits are available in the credit pool, and retrieving the one or more credits from the credit pool, if the one or more credits are available in the credit pool. The method may further include releasing the one or more credits to the memory channel. The one or more released credits are used to perform the memory operation.

Mechanism for facilitating power and performance management of non-volatile memory in computing devices

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Forest Grove, OR, United States of America

Richard Paul Mangold