Intel Corporation

Richard P Vireday

Randy C Steele

Jay J Sturges

Gregory B Hibdon

A deterministic method and apparatus for defining the size and switch assignments of a switch matrix. The method operates on a switch matrix having a number of inputs (N) and a number of outputs (M). When constructing the switch matrix, there will be M columns in the matrix. The method determines a minimum number of rows (R) for the switch matrix. The resultant general purpose R.times.M switch matrix allows any combination of a subset of the N inputs, with up to M members, to be assigned to the outputs. The resultant R.times.M switch matrix will be smaller than an N.times.M switch matrix.

Deterministic method and an apparatus for minimal switch circuits

A deterministic routing method for switch matrices. The routed matrix receives N input signals and produces M output signals on M output columns. The method of the present invention has three steps. First, each of the M output columns in the switch matrix is searched for each of N separate input signals. Secondly, each of the N inputs is assigned to its located column. If all of the N inputs cannot be assigned to one of the M columns, the set of inputs is shifted and the steps are repeated until all of the N inputs are routed.

Deterministic routing method for minimal switch circuits

A programmable gate array comprised of a number of configurable functional blocks. Each configurable functional block has a number (m) of inputs. A global interconnect matrix interconnects the configurable functional blocks. The global interconnect matrix provides for routing any combination of signals entering the matrix to any configurable functional block, up to and including the maximum number (m) of inputs of a configurable functional block. Each configurable functional block includes a product term array connected to the m inputs. The product term array can perform a logical AND of up to m bits. A compare term array is also connected to the m inputs. The compare term array can perform an identity compare of up to m/2 bits. A number n of macro cells are provided in each configurable functional block wherein the number n is less that the number m. An allocation circuit allocates the outputs of the compare term array and the product terms to a macro cell, any compare term being allocable in place of a product term to the macro cell.

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Cameron Park, CA, United States of America

Richard P Vireday