Analog Devices,inc.

Richard P Schubert

Wei An

Mariko Medlock

James M Wilson

Yosef Stein

Antonio J Montalvo

Christopher Mayer

Colm J Prendergast

Brian Reggiannini

A receiver apparatus models and corrects the frequency-dependent and the frequency-independent mismatches between I and Q paths jointly by polynomial estimations. The receiver apparatus may sample digitized I and Q path signals. The sampled data point may be modeled in equations with real and imaginary components. The sampled discrete time-domain data may be converted to frequency-domain data. Multiple statistics values based on the frequency-domain data may be computed. Coefficients for the polynomial equations may be estimated based on the computed statistic values. The channel mismatches may be estimated from the polynomial equations and used to compensate the mismatch either on the I path or the Q path.

Real-time I/Q imbalance correction for wide-band RF receiver

Apparatus and methods for analog-to-digital conversion of quadrature receive signals are provided herein. In certain implementations, a transceiver system includes at least a first pair of analog-to-digital converters (ADCs) associated with a first quadrature receiver channel and a second pair of ADCs associated with a second quadrature receiver channel. The first and second pairs of ADCs can provide analog-to-digital conversion of the same receive signal, but can have different noise profiles relative to one another, such as a low pass noise profile and a band pass noise profile. The transceiver system can further include a reconstruction filter for combining the outputs of at least the first and second pairs of ADCs to generate output signals associated with a lower overall noise profile relative to that of either pair of ADCs alone.

Apparatus and methods for wide bandwidth analog-to-digital conversion of quadrature receive signals

In an example, there is disclosed a system and method for detecting and correcting error in a quadrature receiver (QR). The QR may include a receiver channel operable to divide a received RF signal into I and Q channels. The receiver channel may include error sources, such as (in sequence) pre-demodulation (PD) error, LO mixer error, and baseband (BB) error. Test tones may be driven on the receiver channel at a plurality of test frequencies, and a quadrature error corrector may be provided to detect error from each source. Upon receiving an RF signal, the quadrature error corrector may apply correction coefficients to correct each source of error in reverse sequence (BB, LO, PD).

Quadrature error detection and correction

System and method quadrature error detection and correction

One example embodiment provides a system, apparatus, and method for using polynomial models in tone calibration for quadrature error correction in I/Q receivers. In one example embodiment, method for calibrating an I/Q receiver is provided and includes receiving a first mismatch parameter indicating a mismatch between I and Q channels of the I/Q receiver; and estimating a second mismatch parameter from the first mismatch parameter using a polynomial model.

Quadrature error correction using polynomial models in tone calibration

Apparatus and method for performing a high-speed, low-power bit-wise comparison of two digital words. For each bit, a bit comparator is shown, employing a compare node and a discharge node. After both nodes are charged, the discharge node is discharged and the condition of the compare node signals the result of the comparison. For each bit, a bit comparator is provided including a single transistor switch across the compare node and the discharge node. An exclusive-OR circuit connected to receive the corresponding bits of the words drives and selectively actuates the switch when the values of the corresponding bits are mismatched. Words may be segmented such that comparisons may be done segment-wise and the detection of a mismatch in any segment obviates the discharging of the compare node in segments containing more significant bits, to save power.

Low-power, high-speed word comparator

A digital processor with a cache that provides fast and low power operation. The cache contains a tag array and a data array. The tag array indicates whether a value is stored in the cache for a particular external address. Access to the data array is necessary to determine the actual value. Access of the data array overlaps access to the tag array. Access to the data array includes a step in which the charge stored on column lines corresponding to multiple ways within the data array is altered based on information stored in the memory. This step occurs while the tag array is being operated. Access to the data array includes a second step of sensing one of the state of charge on a selected column line. Sensing occurs after the value has been read from the tag array and the value in the tag array is used to indicate which, if any way in the data array to sense. Processors using this approach quickly read information from the cache, but consume small amounts of power and are therefore well suited for use in cellular telephones and portable electronic devices.

Cache memory with reduced power and increased memory bandwidth

Methods and apparatus are provided for achieving low latency for high priority tasks in digital processing systems. A digital signal processor includes a core processor and a level one memory. In some embodiments, a store buffer is configured to hold write information for the level one memory and for a level two memory. A write buffer is configured to hold write information, received from the store buffer, for the level two memory. The write buffer has a normal capacity and an excess capacity. A memory controller enables the excess capacity of the write buffer when a high priority task is being serviced and inhibits write access to the excess capacity of the write buffer when a high priority task is not being serviced. In other embodiments, the digital signal processor includes first and second fill buffers configured to hold read data in a fill operation. The memory controller steers low priority read data to the first fill buffer or the second fill buffer based on priority of the fill operation.

High/low priority memory

An electronic memory device includes at least one memory cell, a write circuit that defines an output node and mediates a discharge associated with a write operation flowing to the output node, and a write strength selection circuit that modifies at least one characteristic of the discharge. A method for testing data retention of an electronic memory device includes providing a write circuit, storing a value in at least one memory cell of the memory device, directing a weak write operation to the at least one memory cell, and sensing the memory cell to determine if the stored value changed in response to the weak write operation.

Memory cell testing feature

A first device comprises a loop circuit to control a sample rate of a digital circuit element. A circuit comprises a digital loop circuit to control a sample rate of a digital circuit element to be a function of a frequency of a signal received by the circuit. A second device receives two or more sampled data streams having sample rates different from one another, converts the sample rate of one or more of the data streams to provide two or more data streams having sample rates compatible with one another, and combines the two data streams. Sample rate converter devices are used in a PLL and a clock recovery circuit.

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Medfield, MA, United States of America

Richard P Schubert