Nortel Networks Corporation

Other

Avaya Inc.

Richard P Modelski

Michael J Craren

Adrian M Kristiansen

Richard L Angle

Geoff B Ladwig

Benjamin J Brown

John P Roy

John R Edwards

A multi-thread packet processor which processes data packets using a multi-threaded pipelined machine, wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The multi-thread packet processor transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The multi-thread packet processor includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.

Multi-thread packet processor

A method performs a plurality of filter operations on a data packet using an instruction. The method receives an instruction to filter at least one data packet. The method retrieves a filter result based on the received instruction. The method then performs a plurality of filter operations on the at least one data packet in accordance with the retrieved filter result.

Method and apparatus for performing filter operations on data packets using an instruction

A method monitors a network. The method receives at least one data packet, and reads an entry of a memory device. The entry of the memory device containing a first statistical value and a second statistical value. The method determines a third statistical value based on at least one of the data packet, the first statistical value, and the second statistical value. The method then stores the determined third statistical value in the entry of the memory device.

Method and apparatus for monitoring a network using statistical information stored in a memory entry

Route switch packet architecture processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The route switch packet architecture includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.

Method and system for sharing a computer resource between instruction threads of a multi-threaded process

A shift left with carry instruction minimizes the number of instructions required for implementing a binary search. A multi-thread packet processor transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator, wherein the analysis machine implements a binary search by executing a shift left with carry instruction to minimize the number of instructions required for the binary search. The multi-thread packet processor includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.

Load-shift carry instruction

A method performs a radix search data structure. The method selects a reference table based on a value of a selectable parameter. The reference table includes at least one of a valid reference table and a transition reference table, and contains a set of data bits. The method receives a key containing a set of data bits. The method indexes the reference table using at least a subset of data bits in the key. The method determines a result index based on at least a subset of data bits in the reference table. The method then indexes a result table based on the result index to reference a result of a radix search data structure.

Method and apparatus for performing a radix search by selecting one of a valid table and a transition table

A bit field direct manipulation device which processes data packets using a multi-threaded pipelined machine, wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The multi-thread packet processor transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The multi-thread packet processor includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.

Bit field manipulation

Global access bus architecture includes a master request bus and a slave request bus separated from each other and pipelined. The global access bus architecture includes packet input global access bus software code for flow of data packet information from a flexible input data buffer to an analysis machine, packet data global access bus software code for flow of packet data between a flexible data input bus and a packet manipulator, statistics data global access bus software code for connection of an analysis machine to a packet manipulator, private data global access bus software code for connection of an analysis machine to an internal memory engine, lookup global access bus software code for connection of an analysis machine to an internal memory engine, results global access bus software code for providing flexible access to an external memory, and results global access bus software code for providing flexible access to an external memory.

Global access bus architecture

An external memory engine selectable pipeline architecture provides external memory to a multi-thread packet processor which processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator.

External memory engine selectable pipeline architecture

A memory interface for a switching router in a network communications system. The interface operates at 200 MHz PLL clock using high speed transistor logic I/O buffers. The interface allows transfer of clock synchronization signals along with the data signals. This allows the setup/hold times to be optimized for an inbound or outbound data pipeline. During writes, data is at least driven one clock cycle after the address. The interface provides flexibility by utilizing at least two clock cycles in order to accommodate a myriad of memory devices (e.g., burst mode SSRAMs having HSTL I/O). In operation, most of the data transfers through the interface are either direct reads or lookup reads. The interface stores writes are stored in a buffer in order to reduce bus turn around penalties.

High speed physical circuits of memory interface

A high speed access bus interface for a communications network. The interface allows uni-directional transfer of data packets at a fast path processing rate of about 10 gigabits per second. The interface uses a master port and a slave port in a chip to chip data transfer scheme. The master and slave ports may have one or more than one data channel for transferring data packets. The master port includes a clock signal for synchronizing the transfer from the master port to the slave port. The slave may send an asynchronous signal to the master port in order to initiate the master port to stop or stall the pipeline transfer of data packets until space is made available in the slave port buffer. In addition to the clock synchronization, the interface utilizes an enable signal, a start of packet signal, an end of packet signal, an error signal (if necessary), a last valid byte signal, and a parity bit signal to identify, address, each data packet in the data stream. If a processing error occurs, the master port error signal to the slave port also initiates the slave port to disregard the previous data packet. The operating frequency of 50 MHz allows the data packet transfer to exceed 10 gigabits per second.

High speed access bus interface and protocol

A memory access processor and memory access interface for transferring data information to and from a plurality of SSRAM locations. The processor has a lookup controller for identifying a data request and locating the data requested from the SSRAM locations. The bus allows a data request and retrieval throughput from a routing processor to the memory access processor at a maximum rate, about 10 gigabits per second without substantial pipeline stalls or overflows.

Centralized look up engine architecture and interface

A switching router memory map is organized as 64-bit wide double words. The bi-directional data bus is only 32-bits wide, so the Least Significant Words (LSW) are mapped to the even addresses and the Most Significant Words (MSW) are mapped to the odd address. When the host writes to the even address the 32-bit data is stored in the bidirectional data bus buffer. When the host writes to the odd address the entire 64-bit double word access is posted to the appropriate global access bus. When a read operation is performed from an even address the entire 64-bit double word access is performed by the appropriate global access bus. The LSW is available on the bi-directional data bus address data pins and the 32-bit MSW is buffered within the bi-directional data bus. The host can access the MSW by performing a read from the odd address.

Extended double word accesses

External memory engine selectable pipeline architecture provides external memory to a multi-thread packet processor which processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The route switch packet architecture includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.

A method performs a radix search data structure. The method receives a key containing a set of data bits. The method determines a reference index based on a first subset of data bits in the key. The method indexes a reference table based on the reference index to locate a reference field. The method determines a result index based on a second subset of data bits in the key and the reference field. The method then indexes a result table based on the result index to locate a result of a radix search data structure.

Growing community of inventors

Hollis, NH, United States of America

Richard P Modelski