Honeywell G.m.b.h.

Honeywell International Inc.

Richard P Himmer

Jethro F Steinman

M Gulam Kanji

Pankaj H Mody

John J Rosa-Bian

Jeffrey B Scott

Irina Radomy

John J Herman

Yahia C Chehadeh

This software invention requires that information be saved with each object that is placed in a source control system. This information includes the name, type, status, version number, and references to parent objects. When the object is checked-out, this information is used to determine the legality of checking-out any dependent objects. A method is used to generate the information that is saved and another method is used to determine which objects need to be checked-out. The dependent objects that need to be checked-out are then automatically checked-out.

Determination of dependent objects by a source control system and a method to automatically include those objects with the parent object when changes are enabled

For use in a digital process controller (DPC), a system for, and method of, balancing a control algorithm processing load and distributing the load over a given time interval and a real time plant control system employing the system or the method. In one embodiment, the system includes: (1) a model for estimating execution time of at least one control algorithm based on configuration data applied to that algorithm, the DPC capable of balancing and distributing the load based on the estimate generated by the model and (2) a data entry process, associated with the model, that allows an empirically-determined execution time to be associated with at least one control algorithm, the DPC capable of balancing and distributing the load based on the time in lieu of the model based estimate and balancing and distributing the load upon configuration of at least one control algorithm.

System and method for balancing and distributing control algorithm processing load and real time plant control system employing the same

A system for, and method of, achieving heterogeneous data flow between first and second algorithm blocks in a control system, and a distributed, real-time process control system employing the system or the method. In one embodiment, the system includes: (1) a passive connection, associated with a control module containing the second algorithm block, that provides for the communication of data from the first algorithm block to the second algorithm block without requiring the allocation of connector resources within the second algorithm block; and (2) an active connection, associated with the second algorithm block, that provides for the communication of data from the first algorithm block to the second algorithm block using dedicated connector resources within the second algorithm block, the control system thereby capable of providing data to the second algorithm block through both passive and active connections.

System and methods for achieving heterogeneous data flow between

A system for, and method of, providing encapsulated and performance-efficient data references in an object-oriented controller and a distributed, real time process control system employing the system or the method. In one embodiment, the system includes: (1) a client algorithm block that generates a request for an address to enable the client algorithm block to gain direct access to data stored at the address and (2) a supplier algorithm block, that receives and evaluates the request and: (2a) if the supplier algorithm block grants the request, communicates the address to the client algorithm block, allowing the client algorithm block to gain direct access to the data and (2b) if the supplier algorithm block denies the request, withholds the address, forcing the client algorithm block to gain indirect access to the data.

System and methods for providing encapsulated and performance-efficient

When an interlock trip condition occurs, a back tracing of interlock logic occurs by examining input signals to an output gate of the interlock logic to determine which input signal caused the interlock trip condition. If the input signal is a predetermined interlock condition, that signal is deemed to be the cause of the interlock trip, saved and displayed. If the input signal is the output of another gate, then the inputs to that gate are examined to determine which input signal caused that gate to switch state. This process is repeated until a predetermined interlock condition is found which has switched state. By knowing the structure of the interlock logic and knowing the state of logic signals outputted from the interlock logic, the determination is made and saved such that even if the predetermined interlock condition that caused the interlock trip subsequently changes state as a result of placing the device in a safe state, the cause of the interlock trip is ascertained and saved by this method.

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Blue Bell, PA, United States of America

Richard P Himmer