Stmicroelectronics S.a.

Sgs-thomson Microelectronics S.a.

Stmicroelectronics Gmbh

Stmicroelectronics (crolles 2) Sas

Stmicroelectronics S.r.l.

Centre National De La Recherche Scientifique

Sgs-microelectronics S.a.

France Universite D'aix-marseille

Universite De Paris Sud (paris Xi)

Richard P Fournel

Cyrille Dray

Philippe Candelier

Jean Lasseuguette

Francedillaois Pierre Tailliet

Christophe Frey

Sébastien Barasinski

Philippe Gendrier

Daniel Caspar

Fabrice Marinet

Mathieu Pierre Lisart

Jean-Pierre Schoellkopf

Laurent Sourgen

Serge Fruhauf

Thomas Skotnicki

Philippe Boivin

Didier Dutartre

Arnaud Regnier

Francois Jacquet

Jean-Michel Mirabel

Frédéric Gianesello

Francois Tailliet

Pierre Dautriche

Nicolas Hotellier

Claude Chappert

Vincent Fiori

Sigrid Thomas

Eric Mazaleyrat

Romain Laffont

Thibaut Devolder

Maryse Paoli

Rachid Bouchakour

François Guyader

Sylvie Bruyere

Laura Varisco

Pascal Ribot

Pascal Masson

Phillipe Gendrier

Leila Sedjai Aitouarab

Le&iuml;la Sedjai Aitouarab

Emmanuel Vincent

Cedric Maufront

Joo-Von Kim

Sébastien Poirier

Virginie Bidal

Yves Dodo

An electronic device has a rear plate that includes a substrate rear layer, a substrate front layer and a dielectric intermediate layer between the substrate rear and front layers. An electronic structure is on the substrate front layer and includes electronic components and electrical connections. The substrate rear layer includes a solid local region and a hollowed-out local region. The hollowed-out local region extends over all of the substrate rear layer. The substrate rear layer does not cover at least one local zone of the dielectric intermediate layer corresponding to the hollowed-out local region.

Electronic device with hollowed-out rear plate

A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array.

Method for manufacturing a semiconductor chip stack device

A method for forming through vias connecting the front surface to the rear surface of a semiconductor substrate, including the steps of: forming openings in the substrate, thermally oxidizing walls of the openings, filling the openings with a sacrificial material, forming electronic components in the substrate, etching the sacrificial material, filling the openings with a metal, and etching the rear surface of the substrate all the way to the bottom of the openings.

Method for forming electric vias

A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.

Non-volatile reprogrammable memory

A one-time programmable, dual-bit memory device comprises one MOS storage transistor having a semiconductor substrate, first and second active regions formed under the surface of the substrate being separated by a part of the substrate forming a channel region, a gate formed on the surface of the said substrate in line with the channel region and whose respective distal ends are aligned with a part of the first active region and with a part of the second active region, respectively, which gate is permanently held at ground potential, and a gate oxide layer running between the gate and the surface of the substrate. The intact or broken down state between the gate and the first active region determines a stored value of a first bit, and the intact or broken down state between the gate and the second active region determines a stored value of a second bit.

One-time programmable memory device

A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in the at least one code block. The method further includes, when the number of errors exceeds one, modifying a parameter of the read by a chosen value, and performing a reading and decoding of the at least one code block again to obtain a new error information item.

Method of detecting and correcting errors for a memory and corresponding integrated circuit

A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.

Magnetic random access memory array having bit/word lines for shared write select and read operations

The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.

Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane

A magnetoresistive memory element including a trapped magnetic region and a free magnetic region separated by a barrier layer. The free magnetic region comprises a stacking of at least two antiferromagnetically-coupled ferromagnetic layers, a layer magnetic moment vector being associated with each layer, the resulting magnetic moment vector, equal to the sum of the layer magnetic moment vectors, having an amplitude smaller than at least 40% of the amplitude of the layer magnetic moment vector of maximum amplitude. The anisotropy field and/or the demagnetizing field tensor is not identical for the at least two ferromagnetic layers, whereby the angular deviations of the layer magnetic moment vectors are different at the time of the application of an external magnetic field, which enables at least two methods for directly writing into the memory element, as well as its initialization.

MRAM element

A memory cell of the SRAM type is provided that is capable of storing one datum in a non-volatile manner. The memory cell includes two inverters (and) configured as a flip-flop for storing one bit. Each inverter includes a transistor (or) of a first type and a transistor (or) of a second type. The concentration of carriers in the conduction channel of the transistor () of the first type of one of the inverters () is different from the concentration of carriers in the conduction channel of the transistor () of the first type of the other inverter () so that the inverters have different threshold voltages.

Pre-written volatile memory cell

An SRAM memory cell includes first and second inverters () interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors () connected in series between a DC voltage supply source and a grounding circuit (). A circuit () programs the MOS transistors by causing an irreversible degradation of a gate oxide layer of at least some of the transistors ().

Nonvolatile SRAM memory cell

An interface circuit for transforming a first signal varying between a low voltage and a high voltage into a second signal varying between a lower voltage and a higher voltage, the lower voltage being smaller than the low voltage and/or the higher voltage being greater than the high voltage, comprising: an inverter circuit receiving the first signal and being connected for its supply between said higher voltage and said lower voltage, one at least of these connections being performed via at least one diode, a conversion element supplied between said higher and lower voltages, and receiving the output of the inverter circuit and providing the second signal, a storage element capable of maintaining the output of the inverter circuit at said higher or lower voltage when the first signal is respectively equal to the low or high voltage.

Circuit for transforming signals varying between different voltages

A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.

Memory architecture with segmented writing lines

A method for programming a read-only memory cell including a transistor whose source and drain, which have a second type of doping, are formed in a semiconductor substrate with a first type of doping, includes a step of carrying out a contradoping in a region of the source, the region being adjacent to the conduction channel, to make it a region with the first type of doping so as to prevent a transistor effect from occurring.

Methods for programming read-only memory cells and associated memories

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Trets, France

Richard P Fournel