Honeywell Information Systems Inc.

Other

Bull Hn Information Systems, Inc.

Honeywell Bull, Inc.

Richard P Brown

Thomas F Joyce

Arthur Peters

Richard A Lemay

George J Barlow

William E Woods

Philip E Stanley

Steven S Smith

Virendra S Negi

David E Cushing

John L Curley

G Lewis Steiner

Arnold J Smith

Eugene Nusinov

Llewelyn S Dunwell

Amy E Gilfeather

Sharon Sageman

Glenn S Hopkins

The present invention comprises novel methods for the use of compositions comprising 7-keto DHEA for treating psychiatric conditions. These methods include administering an effective amount of a composition comprising 7-keto DHEA in an acceptable carrier, alone or in combination with other psychiatric drugs, such as analgesic agents, anticonvulsants, anti-anxiety agents, antidepressants, anti-panic agents, antipsychotic agents, bipolar agents, psychostimulants to reduce or ameliorate symptoms of a psychiatric condition. This method may be used alone or as an adjunctive treatment for treating a wide variety of psychiatric conditions such as stress disorders, anxiety disorders and depressive disorders.

7-keto DHEA for psychiatric use

A bookcase has an easel pivotally attached to the back of the bookcase housing . The easel is attached to the bookcase using friction supports having additional support members or hinges having hinge pins therein. At least one support member is provided for fixedly holding the planar work surface at the desired angle. Also provided is a raised edge element for supporting work materials upon the planar work surface when in an angled position. Additionally, there is provided a centrally positioned removable rail that can support additional work materials . The bookcase has a plurality of shelves mounted therein along with a plurality of casters fixedly attached to its underside.

Mobile workstation storage device

A holder for implements such as a mortal board, which is to be horizontally positioned, knives, such as broad, spackle, and shear knives, which are to be positioned at an angle, and a roll of drywall tape, vertically positioned. Holder comprises a back plate to secure implements, and a second plate in which the implement holder is temporarily attached to the user, more specifically, the waist area of the user. The mortar board is inserted into the Y-shaped slots which are horizontally aligned to the back plate and are disposed in spaced relationship. The knives are inserted into the compression loaded slots having adjacent relationship and positioned at an angle from the back plate. The tape is inserted into the J-shaped hook which is spaced away from the back plate to allow for the tapes positioning and removal to and from the implement holder. The parts which comprise the implement holder are made from a rigid material, preferably aluminum. When the implements are engaged in their appropriate locations within the implement holder, both hands of the worker are free to conduct other operations.

Implement holder

The emulator includes first and second pipelined stages connected through a bidirectional bus for executing source instructions normally executed by a different/source computer in a highly overlapped manner. The first stage includes an emulator chip which performs the function of fetching and decoding each source instruction stored in cache memory resulting in the generation of a number of vector addresses required for executing the instruction by the second stage. The second stage includes a high performance microprocessor chip having on-chip instruction and data caches for storing a plurality of emulation subroutines and data fetched during subroutine execution. In pipelined fashion, the emulator chip fetches and decodes each source instruction which generates a vector branch address which is loaded into the branch vector register while the microprocessor chip fetches and executes emulation subroutines specified by the vector address transferred via the bus for each previously decoded source instruction.

Emulation of CISC instructions by RISC instructions using two pipelined

A system includes first and second processing units which are interconnected by a bidirectional bus. The first processing unit is a microprocessor chip programmed for executing procedures stored in an on-chip instruction cache unit. The second processing unit receives requests from an external source such as a system bus. The microprocessor chip includes a branch vector facility which connects to the bus. The second processing unit in response to an external request, generates a vector branch address. The processing unit transfers the vector branch address to the branch vector facility for storage along with setting a write indicator. The microprocessor chip, upon detecting that the write indicator was set, branches to the procedure specified by the branch vector address for executing the instructions of the procedure to carry out those operations required for processing the external request or event.

External procedure invocation apparatus utilizing internal branch vector

A data processing system includes a logical address to a physical address translator in an extended memory management unit. A 128 word memory stores task segment descriptor words which include a base address. A 16 word memory stores corresponding present bits to indicate if the addressed task segment descriptor is present in its memory. This arrangement allows a 128 word memory to be cleared in 16 memory cycles.

Segment descriptor present bit recycle and detect logic for a memory

A translator is organized to include at least a pair of content addressable memories (CAMs), each for storing a different portion of the total number of bits of each of the words to be translated. The outputs from each CAM are logically combined within a multiple input random access memory (RAM). Both CAMs are interrogated simultaneously and deliver the results of comparing the word portions of an input word and the CAM contents to the RAM in substantially less time then required for a single CAM memory. The results are logically combined with in the RAM which, in response to a match condition, delivers the results of the translation as an output.

High speed high density dynamic address translator

A priority resolver for providing unambiguous resolution of requests among competing processes vying for access to a common device and which is adapted to a non-distributed environment.

Two stage selection based on time of arrival and predetermined priority

A cache memory for use in a data processing system wherein data words identified by even address numbers are stored separately from data words associated with odd address numbers to enable the simultaneous transfer of two successively addressed data words to or from the cache memory by the transferring of a data word associated with an odd address number and a data word associated with an even address number.

Odd/even bank structure for a cache memory

A cache memory wherein data words identified by odd address numbers are stored separately from data words identified by even address numbers. A group of diagnostic control registers supply signals for controlling the testing of the cache within the cache memory to determine the operability of the individual elements included in the cache memory.

Diagnostic subsystem for a cache memory

In a data processing system, a system memory includes first memory modules having a data path of a first bit width and second memory modules having a data path of a second bit width with the first bit width being less than the second bit width. A central subsystem includes a cache memory unit and processing units for initiating requests for data transfers of the second bit width between the system memory and the subsystem processing units. An interface coupling the system memory and the central subsystem for bidirectional data transfers generates, in response to a memory request of a second bit width wherein the requested data is stored in a first memory module, additional memory requests until sufficient data has been retrieved from the system memory to satisfy the central subsystem request. The interface also monitors data transfers between the system processing units and the system memory and transfers the data transfers to the central subsystem in order to update and to retain the integrity of the cache memory in the central subsystem.

Interface for controlling information transfers between main data

In a data processing system, a central subsystem includes a plurality of special purpose processing units with one of the processing units serving as a control processing unit within a central subsystem. The processing units are coupled to a common subsystem bus for the transfer of data, control information, and address information within the central subsystem. Access to the subsystem bus is allocated by a bus control unit which also interfaces the central subsystem with other processing units such as a system memory or system I/O devices that are included in the data processing system.

Local bus interface for controlling information transfers between units

The performance of a scientific ADD instruction is improved by storing the mantissas of both operands in each of two random access memories, selecting the mantissa with the smaller exponent, shifting that mantissa and performing the ADD operation of adding the mantissas in one machine cycle.

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Acton, MA, United States of America

Richard P Brown