Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Agilent Technologies, Inc.

Richard Ortiz

Roy Tsuchida

Dick T Fong

John P Miller

John P Huetter

Walter William Alexander, Iii

Jerry Huang

Gale A Sill

Zane P Westover

Chenmin Zhang

Gregory R Hargis

Duong Xuan Vu

Embodiments of the present invention include a method for providing protected swapping of a peripheral component in a computer system. The method comprises determining a position of a first mechanical retention latch wherein the first mechanical retention latch has an open position and a closed position and is configured to communicatively couple to a computer expansion card slot. Provided the first mechanical retention latch is in the open position, the method further includes filtering power management events and preventing the computer system from powering up. Provided the first mechanical retention latch is in the closed position, allowing the computer system to accept power management events.

System and method for preventing wake on LAN to protect expansion cards

A method of verifying a monitoring and responsive infrastructure of a system is provided and described. The method includes setting a sensor to a simulation mode. Further, a test value is provided to simulate a real value outputted by the sensor. While in the simulation mode, the test value instead of the real value is sent to the monitoring and responsive infrastructure to invoke a response. Moreover, the response to the test value is verified. In an embodiment, the monitoring and responsive infrastructure is compliant with an Intelligent Platform Management Interface specification.

Method of verifying a monitoring and responsive infrastructure of a system

Methods and apparatus for managing circuit tests. In a first embodiment of the invention, a number of electrical characteristics of a number of electrical components which exist in a circuit are identified, and the number of electrical components are then grouped in response to the number of electrical characteristics. Thereafter, and for each group of electrical components, a circuit test which is common to the electrical components of the group is established. When the execution of a test results in a false fail, the test is debugged, and the debugged test is then associated with each other component in its group. Much of a programmer's debug effort is therefore &ldquo;proactive&rdquo; rather than &ldquo;reactive&rdquo;. Preferably, a test history log is maintained for each component group so that previously abandoned test solutions are not repeated as tests are debugged. In a second embodiment of the invention, a number of test parameters of a number of circuit tests created for a number of electrical components which exist in a circuit are identified. Circuit components are then grouped in response to the test parameters rather than in response to electrical characteristics (though some of the test parameters may actually be electrical characteristics). The methods are preferably implemented in software. The methods and apparatus disclosed not only shorten the time required to complete a debug effort (i.e., to insure that tests are stabile), but also insure a greater degree of uniformity among tests which are associated with like electrical components.

Method and apparatus for managing circuit tests

A method and a system for testing integrated devices such as chips used on a printed circuit board. The system includes test logic formed on the chip and coupled to bi-directional input/output pads. The system is capable of testing input pads, output pads, and bi-directional pads by coupling an input test signal from one pad of a pair of pads to the output of a second pad of the pair of pads. If the signal read out of the second pad corresponds to the expected value, the pads may be considered properly connected. The chips may be tested at any stage during chip manufacture, including after forming the die on a wafer, after cutting the die from the wafer and after packaging the die to produce the chip, and after attaching the chip to a printed circuit board. The system and method allow for quick and easy testing of pad connectivity during the manufacturing process, while minimizing the number of extra gates and trace lines on the chip.

Input-output pad testing using bi-directional pads

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Roseville, CA, United States of America

Richard Ortiz