General Electric Company

Richard O Carlson

Homer H Glascock, Ii

Constantine A Neugebauer

Robert J Wojnarowski

Charles W Eichelberger

Lionel M Levinson

Alexander J Yerman

Harold F Webster

James A Loughran

A package for interconnecting a plurality of integrated circuit chips into a functional unit comprising a multilayer substrate having ground and power conducting layers and a frame for holding the chips with their terminal pads on the side of the frame opposite the substrate. Power and ground terminal pads on the chips are coupled to the appropriate potentials via registering conductive feedthroughs passing through the frame and into the substrate into contact with appropriate power or conductive layers in the substrate. Signal pads on the chips are interconnected by means of a conductive layer which is located over the chips on the side of the frame opposite the substrate.

Multi-chip interconnection package

A method of providing a unitary body comprised of two initially separate layers having similar coefficients of thermal expansion involves forming a mat of glass fibers in a configuration suitable for bonding the two layers together, placing the glass mat between them and heating the resulting stack to a temperature at which the individual fibers of the glass mat deform to form a continuous layer of glass which adheres to both layers, after which the stack is cooled to result in the unitary body.

Flexible glass fiber mat bonding method

Solder layers in a semiconductor chip package, which electrically interconnect conductors used to gain electrical access to the electrodes on the semiconductor chip, are subjected to a transverse compressive force in excess of about 2 pounds per square inch. The semiconductor chip package can thereby undergo a marked increase in the number of cycles of heating and cooling before it fails due to increased thermal resistance arising from structural degradation of the solder layers.

Semiconductor chip packages having solder layers of enhanced durability

A silicon circuit board incorporates multiple levels of patterned conductors. First level upper and lower patterned conductors are situated on an insulation-coated, monocrystalline silicon substrate. Upper and lower, high resistivity, polycrystalline silicon layers, in turn, are situated on the first level upper and lower patterned conductors, respectively. Second level upper and lower patterned conductors are situated over the upper and lower polycrystalline silicon layers. Further levels of patterned conductors in the circuit board may be provided by iteratively forming on the board polycrystalline silicon layers and patterned conductors. Conducting feedthroughs in the circuit board provide electrical communication between various patterened conductors.

Low loss, multilevel silicon circuit board

A thermistor suitable for use in a temperature range with a maximum temperature exceeding 400.degree. C. comprises bulk thermistor material with a pair of electrical leads attached to the thermistor material by respective quantities of conductive paste each having a curing temperature substantially in excess of the aforementioned maximum temperature.

High temperature thermistor and method of assembling the same

Contaminant metal residue on an organic passivation layer of a semiconductor device is removed by plasma etching thereof whereby the performance of the device is restored.

Method of restoring semiconductor device performance

A humidity sensitive device is formed of a humidity sensitive material comprised of a magnesium aluminate spinel and titania material. The humidity sensitive device includes various means for applying heat to the humidity sensitive material to purge the humidity sensitive material of foreign substances and also thereby to restore or rejuvenate the characteristics of the humidity sensitive material.

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Scotia, NY, United States of America

Richard O Carlson