International Telesystems Corporation

Richard N Deglin

James J Frimmel, Jr

Thomas Ouellette

John Ramsay

Thomas Quellette

Lester A Potter

This invention provides an improved means for communicating between a central communications or computer processor and a plurality of peripheral devices via a serial interface such as a pulse coded modulation (PCM) bus. The processor sends data via one of two redundant communications channels, such as a PCM bus, to the peripheral devices, each of which is equipped with a data receiving means such as a shift register. These data receiving means check a specific character position of the input data for a pattern which is unlikely to occur at random, such as hexadecimal `7E`. (X `7E` has a bit pattern of 0111 1110.) Whenever the specified pattern is detected, a return pattern is generated in a specified character position of the data stream which is periodically sent back to the processor. As long as these return characters are received, the processor continues to send data via the first communications channel, and the receiving peripheral devices continue to read their data from that channel. When the return pattern is not received, however, the redundance circuit recognizes this fact and switches to the other communications channel. The receiving means on the peripheral devices detect that the special pattern is now being received in the specified character position of the second communications data stream and switch to read data from the second channel. Thus the error-checking features of more complicated and expensive systems are provided without the need for sophisticated processors on the peripheral devices.

Redundancy and buffering circuits

An apparatus for alternate memory addressing of a random access memory (RAM) allows a first processor to write into the memory on a row-by-row basis and a second processor to read out of the memory on a column-by-column basis. The memory is typically divided into a pluralilty of channels into which the first processor writes data for respective channels asynchronously by the use of twin RAMs. While one RAM is written to by the first processor, the second RAM is read from synchronously with automatic address translation.

Alternate memory addressing for information storage and retrieval

A digital voice recording and reproducing device, preferably connected to a telephone network uses a storage RAM to store voice messages and digital signals. An internal processor connected to the storage RAM processes digital signals to and from the storage RAM. A high speed RAM connected to the internal processor receives and transmits digital signals to and from the internal processor. Encoders and decoders encode voice signals into pulse code modulated (PCM) signals to be delivered into the high speed RAM, and decode digital PCM signals from the high speed RAM. A high speed processor (HSP) connected to the high speed RAM delivers signals from a switch to the high speed RAM. An internal processor connected to the switch, high speed RAM (HSP) and the storage RAM controls the input of signals to the high speed processor, to the high speed RAM and to the storage RAM, and controls the output of signals from the storage RAM to the internal processor and the high speed RAM, and then via the switch and the decoders to output means such as telephone lines.

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Reston, VA, United States of America

Richard N Deglin