Nxp B.v.

Richard Morren

Tom Waayers

Evert-Jan Pol

Henricus Hubertus Van Den Berg

Thomas Franciscus Waayers

Joannes Theodorus Van Der Heiden

Johannes Petrus Wilhelmus Van Beers

An integrated circuit comprising: a plurality of on-chip-instrument-modules; a test-controller-module configured to communicate data with the plurality of on-chip-instrument-modules; a functional-module configured to communicate data with the plurality of on-chip-instrument-modules; and an on-chip-instrument-controller. The on-chip-instrument controller is configured to: for each of the plurality of on-chip-instrument-modules, store an access-indicator; and based on a value of the access-indicator for each on-chip-instrument-module, enable the on-chip-instrument-module to communicate with either: the test-controller-module; or the functional-module.

Integrated circuit on chip instrument controller

An integrated circuit comprises a plurality of clock domains (). Test data is shifted into the integrated circuit through a scan chain (). In a test mode a connection is interrupted between a functional output of a first clock domain () and a functional input of a second clock domain (). Test data is applied from the scan chain () to the functional input and a test response is captured into from the functional output. A delay circuit () is used to delay transfer of the test result from the scan cell () to the functional input when the test result is captured in the scan cell (), to ensure that timing differences between the clock domains do not affect the test. Subsequently the test result is shifted through the scan chain.

Testing of an integrated circuit with a plurality of clock domains

A testing circuit has scan chain segments () defined between parallel inputs (wpi[] . . . wpi[N&#x2212;]) and respective parallel outputs (wpo[] . . . wpo[N&#x2212;]). The scan chain segments comprise a bank () of cells of a shift register circuit, a core scan chain portion (), a first bypass path around the core scan chain portion () and a second bypass path around the bank () of cells of the shift register circuit. This architecture enables loading of data in parallel into the core scan chain, or into the shift register (WBR). In addition, each scan chain segment also has a series latching element (), and this provides additional testing capability. In particular, the shifting of data between the latching elements () can be used to test the bypass paths while the internal or external mode testing is being carried out. This testing can thus be part of a single ATPG procedure.

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Waalre, Netherlands

Richard Morren