E2v Semiconductors

Atmel Grenoble S.a.

Atmel Grenoble

Richard Morisson

Jean-Alain Nicolas

The invention relates to an integrated circuit comprising a succession of N identical elementary circuits (CE, CE, . . . CE), juxtaposed in the order of their rank j varying from 1 to N, N being at least equal to 50, and all having to receive two reference potentials Vref and Vsupplied by two conductors. An upstream input of the second conductor is situated geographically on the side of the rank 1 of the succession of juxtaposed circuits, and an upstream input of the first conductor is situated geographically on the side of the rank N of the succession of juxtaposed circuits. This reduces the error in the potential difference applied to the elementary circuits all along the succession, an error that originates from the non-zero resistance of the conductors. The integrated circuit is applicable to analog-digital converters or digital-analog converters with high resolution.

Integrated circuit including a large number of identical elementary circuits powered in parallel

The invention relates to fast, high resolution, analog digital converters, and more particularly those which possess at least one conversion stage of 'flash' type. The converter according to the invention uses N differential amplifiers with four inputs. The amplifier of rank j receives the input voltage to be converted V&#x2212;Von two first inputs, and a reference potential difference on two other inputs. The reference potential difference is obtained between two taps of networks of resistors that are identical operating in parallel and supplied between a high voltage source and a low current source; the taps for an amplifier are respectively a tap Pof rank j of a first network and a tap P'of rank N&#x2212;j+1 of a second network. This reduces the first and second order non-linearity effects due to the fact that the differential amplifiers consume an input current tapped off from the networks of resistors.

Parallel analog-digital converter with dual static ladder

The invention relates to sample-and hold modules, and notably those which are intended to be placed upstream of an analog-digital converter. The sample-and-hold module conventionally comprises a differential pair of transistors, a follower transistor and a storage capacitor. The follower transistor is turned on during a sampling phase by the application of an emitter current by means of a first current switch and can be disabled during a hold phase by the application of a disabling voltage to its base. The sample-and-hold module operates according to the invention with a hold phase beginning at the same time as the end of a sampling phase and terminating before the start of a new sampling phase. Switching spikes are thus avoided at the transition between the end of a hold phase and the start of a new sampling phase.

Sampler blocker protected against switching parasites

The invention relates to current switches using a differential pair of transistors and being able to operate under a low supply voltage Vcc. According to the invention, provision is made for the current switch to include two differential pairs of two transistors each (T, T; T, T), cascaded together, the second pair (T, T) having complementary current outputs (H, Hb) that flip according to the states of the inputs (E, Eb). The first pair (T, T) is connected to a ground (GND) through a current source, supplying a current of value Io and comprising a transistor (Ts) biased by a voltage Vbias, and it is supplied by a voltage equal to N&#xb7;Vbe+Vbias, where N is a whole number (preferably equal to 1) and Vbe is the base-emitter voltage of the transistor (Ts). The second pair (T, T) is connected to ground directly through a resistance (R). The invention can be applied to the on-off control of sample-and-hold circuits, multiplexers, fast low-voltage logic circuits, etc.

Differential transistor pair current switch supplied by a low voltage VCC

The invention relates to a blocking sampler intended in particular to be used upstream of a fast analog digital converter. The blocking sampler comprises two main semi-samplers each having a respective differential input (E, E') and a respective differential output (S, S&#x2032;). With each main semi-sampler is associated a respective auxiliary blocking semi-sampler comprising an auxiliary tracking transistor (T, T&#x2032;) powered by a voltage tapped off from the terminals of the storage capacitor (C&#x2032;, C) of the other main blocking sampler, an auxiliary storage capacitor (Ca, Ca&#x2032;) linked to the output of this auxiliary tracking transistor and an auxiliary current switch (T, T, SC; T, T, SC&#x2032;) controlled in synchronism with the current switch of the main blocking sampler so as to authorize or block the passage of current in the auxiliary tracking transistor. The auxiliary samplers serve to improve the sampling dynamics in the cases where the signal to be sampled varies rapidly.

Differential blocking sampler, in particular for an analog digital converter

The invention relates to fast analogue-to-digital converters having differential inputs and a parallel structure, comprising at least one network of N series resistors with value r and one network of N comparators. The series resistor network receives a reference voltage and is traversed by a fixed current Iand the row i (i varying from 1 to N) comparator essentially comprises a dual differential amplifier with four inputs; two inputs receive a differential voltage VS&#x2212;VN to be converted, a third being connected to a row i resistor of the network, and a fourth input being connected to an N-i row resistor of the network. The resistor network is supplied by a variable reference voltage originating from a servoloop circuit which locks the voltage level of the middle of the resistor network at a voltage equal to the common mode voltage (VS&#x2212;VSN)/2 present at the output of the sample-and-hold module.

Fast analogue-to-digital converter

The invention pertains to a comparison circuit for an analog/digital converter. In order to reduce the effect of the offset voltages of the various comparators of the comparison circuit, voltage followers and a resistor network delivering at its outputs, mean voltages that are the average of those present on outputs of the comparators are linked downstream of the outputs of the comparators.

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Grenoble, France

Richard Morisson