Other

Pageant Technologies, Inc.

Estancia Limited

Pageant Technologies, Inc. (micromem Technologies, Inc.)

Optimer Pharmaceuticals, Inc.

Estancia Limited Providencials

Richard Michael Lienau

James Stephenson

Laurence P Sadwick

Kenneth E Pope

Irene MacInnis

Brent E Boerger

Bonnie L Lienau

An electronic visible light sensor is employed to detect the presence or lack of sunlight. The simple, digital light/dark data from the sensor is fed to electronic circuits which control security and other devices dependent upon day and night status. These circuits are directed and controlled in turn by associated electronic circuits that gather data which measures the length of the solar night, that is, between dusk and dawn, and by deduction, the length of the day. Given that these time periods vary daily and in a regular fashion, the result will necessarily differ by a few minutes each and every day during the 365 day solar year. The resulting day/night time data is used to estimate, with say, a four to ten minute accuracy, taken against the Universal Coordinated Time System, to establish start/stop times, durations and cycles of security and other devices dependent upon the presence or lack of sunlight relative to UCT designated within the universally accepted twenty-four day. These results are fed to the security control circuitry to define control of data to security and other devices.

Faux solar-driven clock

A non-volatile tri-state random access memory device, including a permanent magnetic bit; a write module in functional communication with the permanent magnetic bit and configured to selectably alter the permanent magnetic bit between three magnetic states, a write module including a write coil disposed about the permanent magnetic bit and in communication with a source of electrical power; and a read module in functional communication with the permanent magnetic bit and configured to observe and communicate each of three magnetic states of the permanent magnetic bit, the read module including a read sensor coupled to a read return line.

Tri-state memory device and method

A non-volatile random access memory device. The non-volatile random access memory device may include a magnetic bit, a write/sense, and a read pulse module. The read pulse module may be configured to send a read pulse signal to the magnetic bit. In addition, a write module may be in communication with the write/sense coil and may be configured to thereby change the magnetic bit between a first magnetic polarity state and a second magnetic polarity state. A read module may be in communication with the write/sense coil and may be configured to detect a first characteristic of the write/sense coil when a read pulse signal is delivered to the magnetic bit in the first magnetic polarity state and to detect a second characteristic of the write/sense coil when a read pulse signal is delivered to the magnetic bit in the second magnetic polarity state.

Coil sensor memory device and method

A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein. The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line. Additionally, the integrated circuit may further include a logical AND array and a logical OR array.

Programmable array logic circuit employing non-volatile ferromagnetic memory cells

A ferromagnetic memory cell is disclosed. The cell includes a bit (), made of a ferromagnetic material, having a remnant polarity. The cell also includes a read drive line () coupled to a first portion of the bit (), to feed a current into the bit (). A sense conductor () is coupled to a second portion of the bit (), to receive the current from the bit (). The current conducted through the bit () is responsive to the polarity of the bit (). A method is also disclosed for determining the magnetic polarity of a ferromagnetic bit (). In this method, a bit () is provided that is made of ferromagnetic material and has a remnant polarity. An input current () is fed into the bit () through a read drive line () coupled to a first portion of the bit (). An output current () is received from the bit () through a sense conductor () coupled to a second portion of the bit (). The current conducted through the bit () is responsive to the polarity of the bit (). A variance between the input current () and output current () is then sensed, from which the magnetic polarity of the bit () is determined.

Method and apparatus for reading data from a ferromagnetic memory cell

A memory device. There is a hall effect device, a current source in electrical communication with the hall effect device, a current drain in electrical communication with the hall effect device, a first sensor arm in electrical communication with the hall effect device and current drain, and a second sensor arm in electrical communication with the hall effect device and current drain. The second sensor arm has a higher resistance than the first sensor arm. There is a voltage measurement module in electrical communication with the current drain and configured to provide a signal based on the voltage in the current drain.

Resistive coupled hall effect sensor

A ferromagnetic memory cell is disclosed having a base (), oriented in a horizontal plane, a bit (), made of a ferromagnetic material, and a sense/write line (), positioned proximate the bit () sufficient to detect the directed polarity of the bit when a first current is applied thereto, and to direct the polarity of the bit when a second larger current is applied thereto in a given direction. The bit () has a height that is oriented perpendicular to the horizontal plane of the base, and a polarity that can be directed along the height.

Non-volatile ferromagnetic memory having sensor circuitry shared with its state change circuitry

Programmable array logic circuit whose product and input line junctions employ single bit non-volatile ferromagnetic cells

A programmable array logic circuit macrocell using ferromagnetic memory cells. More particularly, the present invention uses a non-volatile ferromagnetic memory cell to temporarily store binary data. It is an advantage of the invention to have the ferromagnetic memory cells or bits to store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shutdown. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein, thus eliminating &ldquo;write fatigue&rdquo;. The invention provides an integrated circuit, comprising a programmable OR array ( ), a programmable AND array ( ), coupled to the programmable OR array, and a macrocell output circuit ( ). The macrocell uniquely has a ferromagnetic bit ( ) and sensor ( ) coupled to store remnant output signal, and an output buffer ( ), coupled to output the remnant output signal upon receiving an output enable signal. The macrocell may further include a DQ register that contains the ferromagnetic bit. The DQ register may also include a drive coil, which at least partially surrounds the ferromagnetic bit. Drive coils may have a bi-directional current that sets the polarity of the ferromagnetic bit. The bi-directional current may be switched by two sets of transistor pairs (Q and Q ). The two sets of transistor pairs may, in turn, be gated by first and second transistor respectively. The first and second transistors may be responsive to a DATA signal that is received when a CLOCK signal is received.

Growing community of inventors

Pecos, NM, United States of America

Richard Michael Lienau