Rambus Inc.

Other

Xerox Corporation

Intel Corporation

Richard Maurice Barth

Craig Edward Hampel

Frederick Abbott Ware

Ely K Tsern

Donald C Stark

Paul G Davis

Mark A Horowitz

Kevin S Donnelly

John Bradly Dillon

Abhijit Mukun Abhyankar

Jared L Zerbe

Alfredo Moncayo

James A Gasbarro

Billy Wayne Garrett, Jr

Matthew Murdy Griffin

David Nguyen

Bruno Werner Garlepp

Ramprasad Satagopan

Steven Cameron Woo

Bradley A May

Michael P Farmwald

Todd W Bystrom

Donald Victor Perino

Andrew V Anderson

Stefanos Sidiropoulos

Pak Shing Chau

Thomas J Holman

Clemenz L Portmann

Thomas J Sheffler

Richard DeWitt Crisp

Catherine Yuhjung Chen

Abhijit Mukund Abhyankar

John Girdner Atwood, Jr

William Franklin Stonecypher

Haw-Jyh Liaw

Michael Tak-Kei Ching

Andy Peng-Pui Chan

Fredrick A Ware

John G Atwood

Jeffrey D Mitchell

Wayne S Richardson

Peter D MacWilliams

Lawrence Lai

Nancy David Dillon, Legal Representative

Anil V Godbole

Don Stark

Wingyu Leung

Edward Anthony Richley

Paul Michael Farmwald

Jeffrey H Hoel

Winston K Lee

Nancy David Dillon

By Nancy David Dillon

James A Gasborro

James A Gasbarre

Donald Charles Stark

Frederick Abbot Ware

Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.

Controlling DRAM at time DRAM ready to receive command when exiting power down

An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.

Method and apparatus for indicating mask information

A chip includes a receiver circuit that uses a reference voltage to receive a data signal such that a logic level of the received data signal is determined using the reference voltage, and a register to store a value that represents an adjustment to the reference voltage.

Chip having register to store value that represents adjustment to reference voltage

A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.

Memory device having multiple power modes

A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes tuning circuitry within the slave device such that the performance of the memory system is improved.

Method and apparatus for adjusting the performance of a synchronous memory system

A memory device includes a clock receiver, a command interface, and a data interface separate from the command interface. A memory controller provides the command interface with a command that specifies a write operation. After a programmable latency period transpires from providing the command, data associated with the write operation is provided to the data interface by the memory controller. The memory controller provides power mode information that controls transitions between a plurality of power modes, where for each power mode of the plurality of power modes, less power is consumed than the amount of power consumed during the write operation. The power modes include a mode in which the clock receiver is on and the data interface is off; and a mode in which the clock receiver is off and the data interface is off.

Method of controlling a memory device having multiple power modes

A chip includes a transmitter circuit and a register provided to store a value representative of an equalization co-efficient setting. The transmitter circuit includes an output driver configured to adjust an output data signal based at least in part on the equalization co-efficient setting.

Memory controller and method utilizing equalization co-efficient setting

A memory controller has an interface to convey, over a first set of interconnect resources: a first command that specifies activation of a row of memory cells, a second command that specifies a write operation directed to the row of memory cells, a bit that specifies whether precharging will occur in connection with the write operation, a code that specifies whether data mask information will be issued in connection with the write operation, and if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation. The memory controller interface further conveys, over a second set of interconnect resources, separate from the first set of interconnect resource, the write data.

Memory controller for controlling write signaling

Method of operation of a memory device and system including initialization at a first frequency and operation at a second frequency and a power down exit mode

In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.

Memory write signaling and methods thereof

A dynamic random access memory device (DRAM) receiver circuit includes an input to receive a data signal, and also includes decision circuitry to make a decision about the received data signal based on a present sampled data signal and a coefficient value corresponding to at least one of a previously sampled data signals.

System and dynamic random access memory device having a receiver

A semiconductor memory device includes a memory core, a first interface to receive write data from a first set of interconnect resources, and a second interface, separate from the first interface, to receive from a second set of interconnect resources a column address and a first code. The column address is associated with the write data and identifies a column of the memory core in which to store the write data. The first code indicates whether the write data is selectively masked by data mask information. If the first code indicates that the write data is selectively masked, the second interface is to receive data mask information specifying whether to selectively write portions of the write data to the memory core.

Interface for a semiconductor memory device and method for controlling the interface

A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an external clock signal. The control interface receives a command that specifies a read operation to the memory device. The data interface transfers data between the memory device and an external set of signal lines. The delay locked loop circuit, coupled to the clock receiver circuit, to generate the internal clock signal using the external clock signal. The read pipeline circuit provides read data accessed from the memory core to the data interface. The circuit provides the internal clock signal to the read pipeline circuit in response to receipt of the command that specifies the read operation.

Memory device having a read pipeline and a delay locked loop

A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command. The integrated circuit device generates the value from the information representing the timing parameter pertaining to the random access memory device.

System for a memory device having a power down mode and method

Growing community of inventors

Palo Alto, CA, United States of America

Richard Maurice Barth