Texas Instruments Corporation

Richard Mark Prentice

Robert Floyd Payne

Martin J Izzard

Chung San Roger Chan

Woo Jin Kim

Methods and apparatus to provide clock resynchronization in communication networks are disclosed. An example method of clock resynchronization disclosed herein comprises determining a vote based on adjacent samples occurring within a single bit interval in a sampled data stream, wherein the vote comprises an early vote when the adjacent samples indicate a sampling phase of a sampling clock is early relative to a center position in the bit interval and wherein the vote comprises a late vote when adjacent samples indicate the sampling phase is late relative to the center position, tracking a running difference between a number of early votes and a number of late votes in a plurality of votes corresponding to a plurality of adjacent samples, and adjusting the sampling phase when the running difference reaches a threshold.

Methods and apparatus to provide clock resynchronization in communication networks

One embodiment of the present invention includes a data transmission system. The system comprises a data transmitter that provides a plurality of data bits over at least one data line. The data transmitter comprises a clock that provides a clock signal associated with timing for latching the plurality of data bits and a data encoder configured to encode error data associated with the data transmission system in the clock signal.

Data encoding in a clocked data interface

The present invention facilitates clock and data recovery for serial data streams by providing a mechanism that can be employed to detect and adjust operation and timing of clocks. The invention employs a differential analog circuit, using current steering logic, to process center and edge samples and identify an average operation of the clocks. The circuit can identify transitions between adjacent center/edge data samples and determine whether an identified transition is early or late for each bit in a set of consecutive bits of a received serial data stream.

High speed early/late discrimination systems and methods for clock and data recovery receivers

The present invention provides for improved loopback testing of an electronic communications device. The electronic communications device ( ) includes a transmit serializer ( ), a transmit output buffer ( ), a first phase interpolator ( ), a phase locked loop ( ), a second phase interpolator ( ), a receive deserializer ( ), a receive input buffer ( ), and phase adjust logic ( ). The PLL ( ) generates a timing signal in accordance with a reference clock signal ( ). In one mode of operation, the transmit serializer ( ) transmits data for output through the transmit output buffer ( ) in accordance with the timing signal generated by the PLL ( ). In another mode of operation, the phase interpolator ( ) accepts as input the timing signal generated by the PLL ( ). The phase interpolator ( ) then generates an altered timing signal which the transmit serializer ( ) uses to transmits data for output through the transmit output buffer ( ) asynchronously from the timing signal of the receive deserializer ( ).

Self test of an electronic device

A system for encoding control data onto a clock signal includes at least one clock cycle in the clock signal; a first transition in the at least one clock cycle, the first transition is from a first voltage level to a second voltage level, the first transition is in a first location in the at least one clock cycle; a second transition in the at least one clock cycle, the second transition is from the second voltage level to the first voltage level, the second transition has a variable location in the clock cycle; and an encoder circuit for positioning the second transition in the variable location in response to the control data.

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Wylie, TX, United States of America

Richard Mark Prentice