Micral, Inc.

Richard M Mansfield

William F Dohse

Ronald J Larson

A microprocessor access arbitration network which arbitrates among HOLD, RESET and REFRESH request commands by controlling a preempt bus so that a system memory refresh cycle is never delayed by a DMA or bus master operation is described. If a HOLD request is in progress for an operation other than a REFRESH cycle when a REFRESH cycle is initiated, that HOLD request is delayed while the REFRESH cycle proceeds to completion.

Method and apparatus for arbitrating access to a microprocessor having

A direct memory access controller for computer systems in which the data may be manipulated and acted upon during a transfer to and from locations in memory, or from locations in memory to and from input/output devices. For computer systems having data word widths of two or more bytes of data fewer bus cycles are required for data transfers to and from odd address locations in memory.

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Bloomington, MN, United States of America

Richard M Mansfield