Inmos Limited

Richard M Forsyth

Adrian Philip Wise

Brian J Parsons

Saeid Azmoodeh

Peter Malcolm Boffey

Computer appratus includes an instruction execution unit (13) having a plurality of functional units (14,16) each arranged to execute at least part of an instruction and instruction issuing circuitry (10,12) for issuing simultaneously a group of separate compatible instructions to the execution unit (13) the circuitry (12) having means for classifying each instruction in dependence on the or each functional unit required for execution of that instruction and means for testing the classification of successive instructions and selecting a group which according to their classification are compatible for simultaneous issue to the execution unit (13) without conflicting demands on any function unit (14,16) in the execution unit.

System for grouping instructions for multiple issue using plural

A decoder having a plurality of outputs (R.sub.0 -Rn) each associated with a particular output valve is arranged to add together two binary numbers (A, B) and to select one of the outputs in dependence on the result of the sum. The decoder comprises a plurality of logic circuits each arranged to receive respective bits of both first and second binary numbers to be added together. The logic circuits are arranged to provide, for each output value, a respective result in dependence on the logic states of respective bits of binary numbers representing that particular output value of the decoder. The logic means determines when a predetermined condition is satisfied by the results of the logic circuits associated with an output value of the decoder, whereby that output value is selected.

Decoder

A line delay device comprises a memory having RAM cells in two blocks, each cell being connected to a pair of bit lines. Memory locations in one block are addressed sequentially and subject to a data transfer while an equate operation is effected on the bit lines of the other block. The operations are switched alternately between the two blocks. In each accessing cycle, a plurality of locations are addressed in selected rows of each block and the switching between each block is effected without addressing all locations in each row addressed so that the accessing cycle ends in a different block from the starting block and each row used has a plurality of addressed locations.

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Bristol, United Kingdom

Richard M Forsyth