Advanced Micro Devices Corporation

Spansion Llc.

Intel Corporation

Cypress Semiconductor Corporation

Intel Ndtm US LLC

Other

Micron Technology Incorporated

Advanced Micro Device, Inc.

Richard M Fastow

Yue-Song He

Sameer S Haddad

Zhigang Wang

Krishna Kumar Parat

Chi K Chang

Hagop A Nazarian

Mark W Randolph

Lee Edward Cleveland

Timothy J Thurgate

Shane Charles Hollmer

Sheung-Hee Park

Kazuhiro Mizutani

Pau-Ling Chen

Ojas Ashok Bapat

Jens Olson

Xin Sun

Sheung Hee Park

Dong-Hyuk Ju

Xin Sheng Guo

Lei Xue

Khaled Hasnat

Narayanan Ramanan

Wing Han Leung

Sheunghee Park

Prashant Majhi

Yu Nan Sun

Kuo-Tung Chang

Chang Wan Ha

Jiang Li

Qamrul Hasan

Owen W Jungroth

Imran Khan

Xuehong Yu

Chen Liu

Zhi-Gang Wang

Wei Cao

Hyungseok Kim

Violante Moschiano

Hiroyuki Ogawa

Angela Tai Hui

Tommaso Vali

Shenqing Fang

Takao Akaogi

Hiroyuki Kinoshita

Michael Allen Van Buskirk

John JianShi Wang

Aliasgar S Madraswala

Narbeh Derhacobian

Yi He

Wei Zheng

Ravi S Sunkavalli

Daniel Sobek

Zhizheng Liu

Han Zhao

Ming Sang Kwan

Shankar Natarajan

Uday Chandrasekhar

Amol Ramesh Joshi

Shafqat Ahmed

Shivananda Shetty

Johnny Javanifard

Gulzar Ahmed Kathawala

Masaaki Higashitani

Purval Shyam Sule

Tim Thurgate

Harry Kuo

Nga-Ching Wong

Mattia Cichocki

Chuan Lin

Sung-Chul Lee

Chao Zhang

Kelwin Ko

Tio Wei Neo

Pavel Fastenko

Jianshi Wang

Camila Jaramillo

Wing Leung

Arun Thathachary

Cindy Sun

Kenichi Kumatani

Qiang Lu

Steve Tam

Wing-Han Leung

Chee Law

Zheng Wei

Ricardo Basco

Heonwook Kim

Zhan Liu

Amol R Joshi

Guido Luciano Rizzo

Phuong Banh

Loi La

Ben Michael Shoham

Lee Cleveland

Power consumption of sensing circuitry in a NAND Flash device is reduced by reducing the voltage supply to a portion of logic circuits in sensing circuitry. A first power domain provides power to a first portion of the logic circuits in the sensing circuity and a second power domain provides power to a second portion of the logic circuits in the sensing circuitry. The first power domain has a higher voltage than the second power domain.

Method and apparatus to reduce power consumption of page buffer circuitry in a non-volatile memory device

Systems, apparatuses and methods may provide for technology that biases a word line of a block in NAND memory to a first voltage level, biases a source-side select gate and a drain-side select gate of the block to a second voltage level, and issues a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse. In one example, the discharge erase pulse injects holes into pillars of the block and bypasses an erase of cells in the pillars of the block.

Weak erase pulse

An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

Method and apparatus to mitigate hot electron read disturbs in 3D nand devices

A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

Reducing power consumption in nonvolatile memory due to standby leakage current

Method and apparatus to mitigate hot electron read disturbs in 3D NAND devices

Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of conductive layers vertically spaced apart from one another and separated by voids, each of the plurality of conductive layers forming a word line. The memory component can also include a vertically oriented conductive channel extending through the plurality of conductive layers. In addition, the flash memory component can include a plurality of memory cells coupling the plurality of conductive layers to the conductive channel. Each word line can be associated with one of the plurality of memory cells. Associated devices, systems, and methods are also disclosed.

Flash memory components and methods

An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.

Memory arrays with bonded and shared logic circuitry

A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.

Program verify technique for non-volatile memory

Wafer-to-wafer bonding is used to form three-dimensional (3D) memory components such as 3D NAND flash memory with shared control circuitry on one die to access arrays on multiple dies. In one example, a non-volatile storage device includes a first die including a 3D array of non-volatile storage cells and CMOS (complementary metal oxide semiconductor) circuitry. A second die including a second 3D array of non-volatile storage cells is vertically stacked and bonded with the first die. At least a portion of the CMOS circuitry of the first die to access both the first 3D array of non-volatile storage cells of the first die and the second 3D array of non-volatile storage cells of the second die.

Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer bonding

A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.

Block by deck operations for NAND memory

A method, apparatus, and tangible computer readable medium for processing a Hidden Markov Model (HMM) structure are disclosed herein. For example, the method includes receiving Hidden Markov Model (HMM) information from an external system. The method also includes processing back pointer data and first HMM states scores for one or more NULL states in the HMM information. Second HMM state scores are processed for one or more non-NULL states in the HMM information based on at least one predecessor state. Further, the method includes transferring the second HMM state scores to the external system.

Hidden Markov Model processing engine

Embodiments include a method, apparatus, and a computer program product for combining results from multiple decoders. For example, the method can include generating a network of paths based on one or more outputs associated with each of the multiple decoders. The network of paths can be scored to find an initial path with the highest path score based on scores associated with the one or more outputs. A weighting factor can be calculated for each of the multiple decoders based on a number of outputs from each of the multiple decoders included in the initial path with the highest path score. Further, the network of paths can be re-scored to find a new path with the highest path score based on the scores associated with the one or more outputs and the weighting factor for each of the multiple decoders.

Combining of results from multiple decoders

Embodiments of the present invention include an acoustic processing device and a method for traversing a Hidden Markov Model (HMM). The acoustic processing device can include a senone scoring unit (SSU), a memory device, a HMM module, and an interface module. The SSU is configured to receive feature vectors from an external computing device and to calculate senones. The memory device is configured to store the senone scores and HMM information, where the HMM information includes HMM IDs and HMM state scores. The HMM module is configured to traverse the HMM based on the senone scores and the HMM information. Further, the interface module is configured to transfer one or more HMM scoring requests from the external computing device to the HMM module and to transfer the HMM state scores to the external computing device.

Phoneme score accelerator

Various aspects provide for a new combination of non-volatile memory architecture and memory processing technology. A memory cell has a gate node, a source node and a drain node. The gate node is connected to a wordline of the memory, the source node is connected to a local source line of the memory, and the drain node is connected to a local data line of the memory. A channel-based processing component programs the memory cell and inhibits programming of a second memory cell on the wordline of the memory. The channel-based processing component also grounds the local source line and the local data line in conjunction with programming the memory cell, and floats a second local source line and a second local data line connected to the second memory cell in conjunction with inhibiting programming of the second memory cell.

Parallel bitline nonvolatile memory employing channel-based processing technology

Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of memory transistors arranged electrically in serial is configured to control a gate voltage of a pass transistor. The pass transistor, in turn, enables current flow between two metal bitlines of the semiconductor memory architecture. Accordingly, a relative voltage or relative current of the two metal bitlines can be measured and utilized to determine a program or erase state of a transistor of the serial array of transistors. In a particular aspect, a transistor with small capacitance is chosen for the pass transistor, resulting in a fast correspondence of the pass transistor gate voltage/current relative to transistor array current. This can equate to fast read times for the transistor array, based on differential sensing of the two metal bitlines.

CT-NOR differential bitline sensing architecture

Growing community of inventors

Cupertino, CA, United States of America

Richard M Fastow