Cadence Design Systems, Inc.

Apache Design Solutions, Inc.

Richard M Chou

Pinhong Chen

Norman H Chang

Ankur Gupta

Shen Lin

Weize Xie

Miao Liu

Tobing Soebroto

Liqun Deng

Yufeng Luo

Kai-Ti Huang

Chin-Chih Chang

Hendy Kosasih

Disclosed is an approach to implement multi-die concurrent placement, routing, and/or optimization across multiple dies. This permits the multiple dies to be modeled as a single 3D space. Instead of being limited to a 2D plane, a cell can be placed to the area of any of the dies without splitting the netlist beforehand.

Concurrent optimization of 3D-IC with asymmetrical routing layers

Various embodiments implement an electronic design with automatically generated power intent. One or more inputs to a physical electronic design implementation module may be identified for power intent generation for an electronic design. The power intent for the electronic design may be generated by using at least one or more power related characteristics that are determined from at least the one or more inputs for the power intent generation. With the generated power intent, the electronic design may be implemented at least by guiding the implementation of the electronic design with at least the generated power intent while reducing usage of one or more computing resources.

Method, system, and computer program product for implementing electronic designs with automatically generated power intent

Apparatus and method aspects for power gating of an integrated circuit (IC) include providing at least one I/O power pad of an IC with a switch arrangement. The at least one I/O power pad is utilized to control a power signal transfer to at least a portion of the IC.

System and method for power gating of an integrated circuit

An efficient inductance modeling approach for on-chip power-ground wires using their effective self-loop-inductances is disclosed. Instead of extracting the inductive coupling between every two parallel wires and putting this huge number inductance elements into circuit simulation, this technique determines the effective self-loop-inductance for each power or ground wire segment and only generates a circuit with these effective self-inductors for simulation. This approach greatly reduces the circuit size and makes the full-chip power-ground simulation with the consideration of inductance feasible.

On-chip power-ground inductance modeling using effective self-loop-inductance

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Cupertino, CA, United States of America

Richard M Chou