Western Digital Technologies, Inc.

International Business Machines Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Hgst Netherlands, B.v.

Richard Leo Galbraith

Niranjay Ravindran

Weldon Mark Hanson

Travis Roger Oenning

Jonathan Darrel Coker

Iouri Oboukhov

Jonas Andrew Goode

Evangelos Stavros Eleftheriou

Roy Daron Cideciyan

Bruce Alexander Wilson

Thomas Mittelholzer

David James Stanek

Derrick E Burton

Roger William Wood

Ajay Dholakia

Yuan Xing Lee

Ksenija Lakovic

Henry Yip

Todd Carter Truax

Mario Blaum

David Timothy Flynn

Luiz M Franca-Neto

Walter Hirt

Pradhan Bellam

Richard David Barndt

Anthony Dwayne Weathers

Aldo Giovanni Cometti

Ivana Djurdjevic

Shaohua Yang

Bruce Alvin Gurney

Zongwang Li

Neil Smith

Martin Aureliano Hassner

Patrick Braganca

Hideki Sawaguchi

Rehan Ahmed Zakai

Jongseung Park

Gary William Walker

Vinh Hoang

John Thomas Contreras

Joey Martin Poss

Satoshi Yamamoto

Raymond Alan Richetta

Pablo A Ziperovich

John Jeffrey Stephenson

Timothy Joseph Schmerbeck

Rick Allen Philpott

Francois Bernard Dolivo

Michael Joseph Ross

Donald Earl Vosberg

Gregory J Kerwin

Srinivasan Surendran

Eric James Tree

Jihoon Park

Eran Sharon

Idan Alrod

Gordon James Smith

Thomas R Albrecht

Sedat Oelcer

Michael Grobis

Petrus Antonius Van Der Heijden

Daniel Bedau

Pierre-Olivier Jubert

Xiao Z Wu

Ravi J Kumar

Frank Ray Keyser, Iii

Michael Anthony Moser

Alexander M Taratorin

Reto Josef Hermann

Fuminori Sai

Peter John Windler

Joe Martin Poss

Wolfgang H Schott

Robert Andrew Kertis

Kevin Roy Vannorsdel

David Peter Swart

Mark A Nichols

Allen Prescott Haar

Yaw-Shing Tang

Donald Joseph Schulte

Kraig Bottemiller

Patrick C Arnett

Mark Andrew Bergquist

Christian J Goetschel

Richard Michael Brockie

Daniel D Reno

Nyles N Heise

Gregory Scott Bush

Steven Michael Currie

Larry A Navarro, Jr

Paul P Howard

Mark D Warne

Michael J Ross

Ismail Demirkan

Dave James Stanek

Example systems and methods for using synchronization marks to correct insertions and deletions for DNA data storage are described. A data unit may be encoded in oligos that include synchronization marks at predetermined intervals along the length of each oligo. During decoding, the synchronization marks may improve identification and isolation of insertions and deletions for correction of symbol alignment prior to error correction code decoding. In some configurations, correlation analysis may be used to improve isolation of insertions and deletions where multiple copies of the same oligo are available.

Preprocessing for correcting insertions and deletions in DNA data storage

Example channel circuits, data storage devices, and methods for asynchronous sampling from an oversampled analog-to-digital converter are described. The channel circuit may include an analog-to-digital converter configured to generate an oversampled digital signal from an analog data signal using a sample rate that is an integer multiple of the baud rate of the channel circuit. A digital sample interpolator may then interpolate interpolated digital signal values from multiple signal values of the oversampled digital signal and select values at baud rate to generate a baud rate digital signal. The baud rate digital signal may be used by an iterative detector in a timing loop and, once a target timing is achieved, for the iterative detector to detect data bits from the interpolated digital signal.

Channel circuit with asynchronous sampling from an oversampled analog-to-digital converter

Example systems and methods for using nested error correction codes for DNA data storage are described. A data unit may be encoded in a set of oligos. Using an error correction code, such as an LDPC code, a codeword may be determined for the data unit that is a multiple of the data payload capacity of each oligo. The codeword may be divided among the set of oligos, along with corresponding redundancy data. Any number of additional levels of nested error correction codes may be implemented by aggregating sets of smaller codewords into larger codewords and storing the corresponding redundancy data in the set of oligos. Each nested level may be aggregated from the set of oligos and decoded using the corresponding error correction code matrix and set of redundancy data as needed, such as in response to failure to decode codewords at a lower level.

Nested error correction codes for DNA data storage

Example channel circuits, data storage devices, and methods for using zero force adaptation to equalize a read data signal based on known data are described. A known user data signal may be determined during prior read operations and used with a residue term from the equalized read data signal to adapt the tap weights for an equalizer filter using a zero force adaptation algorithm. For example, the known user data signal may be determined by a soft output detector (e.g., SOVA detector) or full or partial decoding by an iterative decoder (e.g., LDPC decoder) and fed back for adapting the equalizer.

Channel circuit with zero force equalizer

Example systems, data storage devices, testers, and methods for storage device configuration using mutual information are described. A data storage device may include channel circuit configuration settings for the encoding and decoding of data written to a non-volatile storage medium. Mutual information metrics may be calculated based on a multi-bit symbol size to compensate for inter-symbol interference and compared to mutual information thresholds to determine the configuration settings, such as bit and track densities, error correction codes, and modulation codes. Mutual information metrics may be used to characterize heads and media independent of the configuration settings.

Data storage device configuration using mutual information

Example systems, read channel circuits, data storage devices, and methods to use a global variance parameter based on mutual information to modify operation of a soft output detector in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector that includes variance terms. The variance terms are modified by a global variance parameter based on mutual information values. The soft output detector processes an input signal using the modified branch variance terms to determine data bits and corresponding soft information for decoding data in the read channel.

Global variance parameter based on mutual information in a data channel

Example systems, data storage devices, testers, and methods for storage device configuration using symbol context mutual information are described. A data storage device may include channel circuit configuration settings for the encoding and decoding of data written to a non-volatile storage medium. The configuration settings may be determined by determining a known pattern for a sector, determining a series of symbol contexts, determining mutual information for each symbol context, and using the symbol context mutual information to determine relationships among configuration settings, such as bit size, error correction code rate, and modulation code. Once determined, the configuration settings may be used to configure the modulation code and ECC rate for the channel circuit of the data storage device.

Modulation code and ECC rate optimization using symbol context mutual information

Example channel circuits, data storage devices, and methods for data read synchronization from phase modulated synchronization fields are described. A data synchronization detector may receive an oversampled digital read signal read from a synchronization field that uses a single written pattern to encode the start of data position, phase, and gain for the read channel. The write pattern may use a phase modulated carrier signal to encode a pseudo-random binary sequence indicating the start of data position.

Data read synchronization from phase modulated synchronization fields in a data storage device

Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix are described. Data units may be read from a storage medium. Multiple sets of parity bits may be available for different data units, different sets of parity bits having a different number of parity bits corresponding to different parity matrices and desired code rates. A primary parity matrix may provide a base code rate and one or more extended parity matrices may provide increased code rates based on additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data units based on the data units from the read signal.

Adjustable code rates and dynamic ECC in a data storage device

Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix based on write verification determining extended parity are described. A data unit with a base set of parity bits may be written to a non-volatile storage medium and then read back for write verification. The data unit may be decoded using the base set of parity bits and corresponding primary parity matrix. Based on the decoding of the write verification read signal, a number of parity bits for an extended set of parity bits may be determined and the extended set of parity bits may be stored to an extended parity storage location for use during subsequent read operations.

Adjustable code rates and dynamic ECC in a data storage device with write verification

A data storage device includes a memory device including a plurality of wordlines, each wordline having a plurality of cells, and a cell statistics generator (CSG) disposed on the memory device. The CSG includes logic configured to receive a plurality of left read senses and a plurality of right read senses for the plurality of cells of a wordline, determine a plurality of first windows and a plurality of second windows, determine a left window sum and a right window sum, determine a deviation parameter and a dispersion parameter based on the left window sum and the right window sum, and determine one or more characteristics of the plurality of cells based on the deviation parameter and the dispersion parameter. The deviation parameter and the dispersion parameter are used to describe a number of errors of the left read sense and the right read sense.

Cumulative wordline dispersion and deviation for read sense determination

Example systems, read channels, and methods provide an oversampled digital phase lock loop for use in a read channel. The phase lock loop receives a digital data signal comprised of oversampled digital signal values with a sample rate that is a multiple of the baud rate of the channel. A set of oversampled digital signal values is selected for each iteration of the phase lock loop to correct the phase of an analog-to-digital converter. The phase lock loop determines a phase gradient, based on an iterative detector, and feeds back a phase correction for the next iteration of the phase lock loop. A baud rate digital data signal is provided to the rest of the channel based on down sampling or interpolated based on the phase gradient.

Oversampled phase lock loop in a read channel

Example systems, read channels, and methods provide states equalization for a digital data signal in preparation for a soft output detector. The states equalizer determines a set of signal values from the digital data signal and filters the set of signal values through a set of finite impulse response filters configured to generate a set of state values for a target signal value, where each filter corresponds to a potential state of the target signal value. Based on the state values, a set of probabilities for possible states is determined and used to populate a decision matrix for a soft output detector.

Trained states equalizer in a read channel

Example control circuitry, data storage devices, and methods to provide a spiral data track format that is different from the underlying servo track format are described. The data storage device may include a storage medium configured with a plurality of tracks in at least one continuous spiral pattern and a head actuated over the storage medium. The data tracks may be written to the storage medium with track lengths that are different than a single revolution of the storage medium.

Offset spiral data track format for data storage devices

Example read channel circuits, data storage devices, and methods to provide overlapping processing of data tracks are described. The data storage device may include media configured with a plurality of tracks in a concentric or continuous pattern. The read signal for a data track may be processed using error correction codes (ECC) as it is read during a first track read operation period. Some portion of its data sectors may need additional ECC postprocessing after the first track is initially received and processed by the read channel circuit. While the read signal for a next data track is being read and processed, the read channel circuit may continue postprocessing of the portion of data sectors from the first track during the second track read operations. Various decision parameters for managing the data stream, additional postprocessing time, and rereading tracks for data recovery are also described.

Overlapping processing of data tracks

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Rochester, MN, United States of America

Richard Leo Galbraith