Intel Corporation

Hewlett-Packard Development Company, L.p.

Hewlett-Packard Company

Richard Lawrence Carlson

Herbert H Hum

Eric J DeHaemer

James R Vash

Leena K Puthiyedath

Brinda Ganesh

Adrian C Moga

Ganesh Kumar

David Bubien

Scott J Erlanger

Michelle M Sebot

Eric R Delano

Leith L Johnson

Eric R DeLano

Charles Regis Morganti

A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Processors having virtually clustered cores and cache slices

A read control system and method for a memory device are provided. One embodiment of a system, among others, includes dump logic coupled to a data source, said dump logic configured to receive a first group of a defined slice of data and a second group of the defined slice of data; and a true dump bus and a complement dump bus configured in a wired-OR arrangement, said dump logic configured to drive the first group of data onto the true dump bus and the second group of data onto the complement dump bus.

Read control systems and methods

Systems, methodologies, media, and other embodiments associated with cache systems are described. One exemplary system embodiment includes an instruction cache comprising single-ported memories. The example system can further include a cache control logic configured to process cache events of different types that may be received by the instruction cache, and being configured with a multi-stage pipeline that coordinates processing of the cache events to the single-ported memories. The multi-stage pipeline can have different stages pre-assigned as read/write stages for the cache events to minimize access conflicts between the cache events.

Instruction cache using single-ported memories

A unified buffer, comprising a shifting queue, receives instructions to be tracked by receiving units in a computer architecture. The receiving units search the unified buffer from the oldest entry to the most recent entry. Status bits in each entry indicate which of the receiving unit(s) the entry is destined for. Existing entries in the unified buffer shift down when a new entry is inserted at the top. Entries may be passed to different receiving units by updating the status bits; and an entry expires after it has been accepted by its final receiving unit.

Unified buffer for tracking disparate long-latency operations in a microprocessor

A common hardware page walker includes an arbitration logic block that controls data bus access between the arbitration logic block and multiple translation lookaside buffers (TLBs), such as an instruction TLB and a data TLB. The arbitration logic block simplifies the complexity within the hardware page walker and makes multiple-state data transfer possible. Each unit (i.e., the hardware page walker and a data TLB and an instruction TLB) has a unidirectional bus that it always drives, and the arbitration logic block informs the hardware page walker which of the busses is active during any given cycle. Thus, the hardware page walker can receive only one command per cycle, and needs no extra logic to handle multiple bus access requests.

Method and apparatus for translation lookaside buffers to access a common hardware page walker

Methods improve state information retention when selecting a not-recently-used element in an array of N elements. A first method comprises the steps of subdividing the array of N elements into K groups, selecting a group from among the K groups, selecting an element that is set to a not-recently-used state from the elements in the selected group, and marking the selected element as recently-used. If all the elements in the selected group are marked as recently-used, the method preferably marks all the elements in the selected group, except the selected element, as not-recently-used. Alternately, the method simply marks all the elements in the selected group when all the elements in the selected group are marked as recently-used. The method also preferably cycles through the groups so that a different group is selected each time. A second method comprises the steps of selecting an element that is marked as not-recently-used from the elements in the array, marking the selected element as recently-used and marking all the elements in the array except the selected element as not-recently-used when all the elements in the array are marked as recently-used. A program that comprises components that execute the above methods is embodied on a computer readable medium.

Retaining state information of an array of elements by subdividing the array into groups of elements

A PC bus architecture that is compatible with an industry standard bus architecture and allows devices to transfer data more effeciently. The protocol of the present invention allows a data transaction in which a data transfer request can be made by a bus master device and then queued so that the transaction occurs at a later time allowing the bus to be free for other transactions until the responding device has prepared the data.

Method for enhanced peripheral component interconnect bus split data

A PC bus architecture that is compatible with an industry standard bus architecture and allows devices to transfer data at higher data rates that the bus clock speed. By transferring data more than once per clock cycle, the data transfer rate is multiplied. Another feature of the present invention is a protocol allowing a data transaction in which a data transfer request can be made by a bus master device and then queued so that the transaction occurs at a later time allowing the bus to be free for other transactions until the responding device has prepared the data.

Growing community of inventors

Fort Collins, CO, United States of America

Richard Lawrence Carlson