Northrop Grumman Systems Corporation

Trw Limited

Northrop Grumman Space & Mission Systems Corporation

Richard Lai

Michael Edward Barsky

Yaochung Chen

Ronald W Grundbacher

Roger S Tsai

Po-Hsin Liu

Harvey Newell Rogers

Mark Kintis

Jeffrey Ming-Jer Yang

Patty Pei-Ling Chang-Chien

Yeong-Chang Chou

Vesna Radisic

William Roland Deal

Yun-Ho Chung

Matt Yuji Nishimoto

Huan-Chun Yen

Jane Lee

Wayne Yoshida

Jennifer Wang

Xiaobing Mei

Weidong Liu

Hsu-Hwei Chen

Stephen J Sarkozy

Linh Dang

Michael Battung

James C K Lau

Rosie M Dia

Ronald Grundbacher

Kevin Masaru Kung Hoong Leong

Quin W Kan

Keang H Kho

Yeong-Chang Choug

Matthew R Parlee

Denise L Leung

Vladimir Medvedev

A field effect transistor (FET) including a substrate, a plurality of semiconductor epitaxial layers deposited on the substrate, and a heavily doped gate layer deposited on the semiconductor layers. The FET also includes a plurality of castellation structures formed on the heavily doped gate layer and being spaced apart from each other, where each castellation structure includes at least one channel layer. A gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer. A voltage potential applied to the gate metal structure modulates the at least one channel layer in each castellation structure from an upper, lower and side direction.

Wrap around gate field effect transistor (WAGFET)

A field effect transistor (FET) device including a substrate and a plurality of semiconductor layers provided on the substrate, where a top semiconductor layer is a heavily doped cap layer and another one of the semiconductor layers directly below the cap layer is a Schottky barrier layer, and where a gate recess is formed through the cap layer and into the Schottky barrier layer. The FET device also includes a gate terminal having a titanium layer, an inhibitor layer provided on the titanium layer and a gold layer provided on the inhibitor layer, where the gate terminal is formed in the recess so that the titanium layer is in contact with the Schottky barrier layer, and where the inhibitor layer is effective for preventing hydrogen gas from being dissociated into hydrogen atoms so as to reduce or prevent hydrogen poisoning of the FET device.

Embedded hydrogen inhibitors for semiconductor field effect transistors

An electronic system. The electronic system includes a waveguide structure having a first waveguide-coupling point and a second waveguide-coupling point and an active electronic circuit having a first circuit-coupling point and a second circuit-coupling point. The second waveguide-coupling point is coupled to the first circuit-coupling point; the system is capable of receiving an input signal at the first waveguide-coupling point and transmitting an output signal at the second circuit-coupling point and/or receiving the input signal at the second circuit-coupling point and transmitting the output signal at the first waveguide-coupling point; the input signal and the output signal have frequencies in a terahertz frequency range; and the system is fabricated as a monolithic integrated structure having the waveguide structure fabricated by micromachining and the circuit fabricated monolithically.

Monolithically integrated active electronic circuit and waveguide structure for terahertz frequencies

In a method of forming a semiconductor device on a semiconductor substrate (), a photoresist layer () is deposited on the semiconductor substrate; a window () is formed in the photoresist layer () by electron beam lithography; a conformal layer () is deposited on the photoresist layer () and in the window (); and substantially all of the conformal layer () is selectively removed from the photoresist layer () and a bottom portion of the window to form dielectric sidewalls () in the window ().

High electron mobility transistor semiconductor device and fabrication method thereof

An InP high electron mobility transistor (HEMT) structure in which a gate metal stack includes an additional thin layer of a refractory metal, such as molybdenum (Mo) or platinum (Pt) at a junction between the gate metal stack and a Schottky barrier layer in the HEMT structure. The refractory metal layer reduces or eliminates long-term degradation of the Schottky junction between the gate metal and the barrier layer, thereby dramatically improving long-term reliability of InP HEMTs, but without sacrifice in HEMT performance, whether used as a discrete device or in an integrated circuit.

High electron mobility transistor (HEMT) structure with refractory gate metal

A common source, bi-directional microwave amplifier is described. More particularly, the present invention is a microwave, common source, bi-directional amplifier that includes a first amplification path and a second amplification path wherein the signal directional flow is controlled through the selective biasing of the first amplification path and the second amplification path. Each amplification path is designed to optimize desired performance. For signal flow through the first amplification path, the first amplification path is biased-on and the second path is biased-off. For signal flow through the second amplification path, the second amplification path is biased-on and the first path is biased-off.

Asymmetric, optimized common-source bi-directional amplifier

Apparatuses ( ), and methods of using same, for the simultaneous thinning of the backside surfaces of a plurality of semiconductor wafers (W) using a non-crystallographic and uniform etching process, are described. The apparatuses ( ) include a fixture ( ) having a plurality of horizontal receptacles ( ) for receiving the semiconductor wafers (W). The loaded fixtures ( ) are then immersed into an etchant solution ( ) that is capable of isotropically removing a layer of semiconductor material from the backside surface of the semiconductor wafers (W). The etchant solution ( ) is preferably heated to about 40&deg; C.-50&deg; C. and constantly stirred with a magnetic stirring bar ( ). Once a sufficient period of time has elapsed, the thinned semiconductor wafers (W) are removed from the etchant solution ( ). The apparatuses ( ) are capable of simultaneously thinning several semiconductor wafers (V) down to a final thickness of about 25 &mgr;m.

Wafer thinning techniques

A method is provided for backside processing a semiconductor wafer ( ) including applying a polymer based protective coating ( ) on the wafer, depositing a barrier layer of ceramic ( ) on the protective coating, and coating the ceramic layer with a thermoplastic based adhesive ( ). Thereafter, the wafer ( ) is bonded to a perforated substrate ( ) and then lapped and polished to a desired thickness and patterned with an etch mask. A high temperature plasma etching process is then used to etch via holes in the wafer ( ). After etching and subsequent backside processing, the adhesive layer ( ) is dissolved in acetone to separate the wafer ( ) from the substrate ( ). The protective coating ( ) is then dissolved with a solvent to separate the ceramic layer ( ) from the finished wafer ( ).

Wafer adhesive for semiconductor dry etch applications

A method of manufacturing a HEMT IC using a citric acid etchant. In order that gates of different sizes may be formed with a single etching step, a citric acid etchant is used which includes potassium citrate, citric acid and hydrogen peroxide. The wafer is first spin coated with a photoresist which is then patterned by optical lithography. The wafer is dipped in the etchant to etch the exposed semiconductor material. Metal electrodes are evaporated onto the wafer and the remaining photoresist is removed with solvent.

Process for forming a large area, high gate current HEMT diode

An enhancement mode FET device ( ) that employs a strained N-doped InAlAs charge shield layer ( ) disposed on an intrinsic InAlAs barrier layer ( ). A gate metal electrode ( ) of the FET device ( ) is controllably diffused through a recess ( ) into the shield layer ( ) to the barrier layer ( ). The resulting enhancement mode device ( ) provides an excellent Schottky barrier with a high barrier height that inhibits undesirable surface depletion effects through charge shielding by the shield layer ( ) in the regions between the recess edge and the gate metal. Minimizing surface depletion effects makes the device more robust by making the surface less sensitive to processing conditions and long-term operation effects.

Enhancement mode device

A single-layer, metal-insulator-metal capacitor, a monolithic microwave integrated circuit including such capacitors, and a process of fabricating such capacitors. The capacitor has a single layer of insulating material between two metallic layers. At least one of the metallic layers has rounded corners, reducing the electric field at the corners, and so lessening the likelihood of breakdown. In one preferred embodiment, each metal layer has rounded corners. The capacitors can be fabricated by an optical lithographic process.

Single-layer dielectric structure with rounded corners, and circuits including such structures

A method for determining the etch depth of a gate recess ( ) in an InP based FET device ( ). The source-drain, current-voltage (I-V) relationship is monitored during the etching process. As the etch depth increases, a kink is formed in the linear portion of the I-V relationship. When the kink current reaches a desired value, the etching is stopped. The kink current is a strong function of etch depth, so small differences in etch depth can be easily targeted. By controlling the etch depth, the characteristics of the transistor can be reproducibly controlled and optimized.

Method for determining etch depth

A field effect transistor with a double sided airbridge comprises a substrate containing a conductive region and source, drain and gate electrodes disposed on the substrate. The gate electrode has a finger portion with a first end secured to the substrate between the source and drain electrodes and a second end, and a double sided airbridge portion flaring outwardly from the second end and having opposed first and second extremities. A first gate pad is disposed on said substrate outwardly from the source electrode and is connected to the first extremity. A second gate pad is disposed on said substrate outwardly from the drain electrodes and is connected to the second extremity. The gate pads serve to support the airbridge gate finger so as to reduce stress on the gate finger. The first and second gate pads receive and transmit signals through the airbridge and to and from the gate finger.

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Redondo Beach, CA, United States of America

Richard Lai