3com Corporation

3 Com Corporation

Richard L Traber

Ramon S Co

Li-Jau (Steven) Yang

Li-Jau Yang

An architecture, method, and apparatus for managing a data buffer (Data Buffer Management DBM). A data buffer within the DBM is an unified linear memory space, and is divided into numbered physical pages with a predetermined page size. A memory map translates logical address spaces for storing/reading DBM transferred data to the physical address spaces. Each packet to be written into DBM is assigned a frame number or frame handler; thereafter, that frame number will be passed by the original owner (a device attached to the data buffer) to different processes for reading out and/or modifying the associated packet or packet data. Frame number assignment is done prior to actual data transfer by request of the data owner. The frame number request is done prior to moving data from the owner's local memory into the DBM's data buffer. Frame number is allocated dynamically by the DBM. Frame number requests, transfer of frame numbers and other admin functions of the transfer are carried out over an M bus and the DMA transfer of data is performed on an F bus, each of which are coupled to the DBM and the attached devices.

Device and method for multi-ported, single bus-mastering data buffer management

An automatic scan test enable signal assertion system and method responds to transitions in signals communicated via selected pins that are not dedicated solely to testing operations. Pins are utilized to communicate a trigger signal and a stage progression signal. The trigger signal provides an indication to initiate a scan test enable signal assertion or deassertion and the stage progression signal controls the progress of the scan test enable activation or deactivation initiation. A scan test enable trigger sensing component provides an assertion or deassertion notification when logical values of a trigger signal captured during multiple stages provide an indication to begin a scan test enable signal assertion or deassertion. A staging component advances the logical values through stages in accordance with a progression signal and issues an asserted or deasserted scan test enable signal based upon the assertion or deassertion notification from the scan test enable trigger sensing component.

Automatic activation of ASIC test mode

A device and method for filtering addresses being transported through a high performance network, and rendering forwarding decisions for data frames corresponding to the address. Such data frames might correspond to multicast addresses wherein filtering is needed to prevent undesired data frames from being uploaded and processed by a receiving machine. The incoming address is hashed into an index for retrieving values from a table with a frame status. If the frame is valid, the same index is used to retrieve a table entry having address and address status information. If multiple data frames have been hashed into the same index, then further filtering is performed by the host machine or a processing device. Otherwise, the incoming address is compared with the address in the table entry. If a match occurs then the data frame is uploaded, and if no match then the frame is discarded. Frame status indicators in a bit register are used to direct actions performed on the frame. Further filtering, uploading, or discarding of the frames can be handled by a host driver, or by an on-board processor on a network interface device or card, via direction from the frame status indicators.

Network address filter device

A phase detector is disclosed that eliminates frequency ripple in a phase-locked loop circuit. The detector includes first and second circuits for providing UP and DOWN signals respectively. It also includes a delay element for setting the duration of the DOWN signal so as to eliminate phase jitter and static phase offset.

Growing community of inventors

Fremont, CA, United States of America

Richard L Traber