Micron Technology Incorporated

Richard L Stocks

Kevin G Donohoe

Kyle K Kirby

Luan C Tran

William Mark Hiatt

Swarnal Borthakur

John K Lee

Hyuntae Kim

Li Li

Ronald Allen Weimer

Chris W Hill

Some embodiments include methods of forming semiconductor constructions in which a semiconductor material sidewall is along an opening, a protective organic material is over at least one semiconductor material surface, and the semiconductor material sidewall and protective organic material are both exposed to an etch utilizing at least one fluorine-containing composition. The etch is selective for the semiconductor material relative to the organic material, and reduces sharpness of at least one projection along the semiconductor material sidewall. In some embodiments, the opening is a through wafer opening, and subsequent processing forms one or more materials within such through wafer opening to form a through wafer interconnect. In some embodiments, the opening extends to a sensor array, and the protective organic material is comprised by a microlens system over the sensor array. Subsequent processing may form a macrolens structure across the opening.

Semiconductor processing methods

Methods for fabricating contacts of semiconductor device structures include forming a dielectric layer over a semiconductor substrate with active-device regions spaced at a first pitch, forming a first plurality of substantially in-line apertures over every second active-device region of the active-device regions, and forming a second plurality of substantially in-line apertures laterally offset from apertures of the first plurality over active-device regions over which apertures of the first plurality are not located. Methods for designing semiconductor device structures include forming at least two laterally offset sets of contacts over a substrate including active-device regions at a first pitch, the contacts being formed at a second pitch that is about twice the first pitch.

Methods for fabricating contacts of semiconductor device structures and methods for designing semiconductor device structures

Methods of filling cavities or trenches. More specifically, methods of filling a cavity or trench in a semiconductor layer are provided. The methods include depositing a first dielectric layer into the trench by employing a conformal deposition process. Next, the first dielectric layer is etched to create a recess in the trench within the first dielectric layer. The recesses are then filled with a second dielectric layer by employing a high density plasma deposition process. The techniques may be particularly useful in filling cavities and trenches having narrow widths and/or high aspect ratios.

Methods for filling trenches in a semiconductor material

A semiconductor device structure includes staggered contacts to facilitate small pitches between active-device regions and conductive lines while minimizing one or both of misalignment during fabrication of the contacts and contact resistance between sections of the contacts. The contacts of one row communicate with every other active-device region and are staggered relative to the contacts of another row, which communicate with the remaining active-device regions. Each contact may include a relatively large contact plug with a relatively large upper surface to provide a relatively large amount of tolerance as a contact hole for an upper portion of the contact that is formed. The contact holes may be formed substantially simultaneously with trenches for conductive traces, such as bit lines, in a dual damascene process. Intermediate structures are also disclosed, as are methods for designing semiconductor device structures.

Semiconductor devices including fine pitch arrays with staggered contacts

Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a terminal and a dielectric layer to at least an intermediate depth in a substrate of a workpiece. The hole has a first lateral dimension in the dielectric layer and a second lateral dimension in the substrate proximate to an interface between the dielectric layer and the substrate. The second lateral dimension is greater than the first lateral dimension. The method further includes constructing an electrically conductive interconnect in at least a portion of the hole and in electrical contact with the terminal.

Microfeature workpieces and methods for forming interconnects in microfeature workpieces

A plasma etching method includes forming polymer material over at least some internal surfaces of a plasma etch chamber and forming polymer material over at least some surfaces of a semiconductor wafer received within the plasma etch chamber. Substantially all polymer material is plasma etched from the chamber internal surfaces while at least some polymer material remains on the wafer. In another aspect, a semiconductor wafer is positioned on a wafer receiver within a plasma etch chamber. A photoresist layer has previously been formed thereon and has openings formed therethrough. First plasma etching is conducted through openings formed in the photoresist layer with a gas comprising carbon and a halogen to form openings in material on the wafer. A first polymer comprising carbon and the halogen forms over at least some internal surfaces of the plasma etch chamber during the first plasma etching. A second polymer is formed over the wafer and relative to the material openings to mask said material within the openings. After forming the first and second polymers and with the wafer in the chamber, substantially all the first polymer from chamber internal surfaces is plasma etched while the second polymer masks the material within the openings.

Plasma etching methods

A method and apparatus for improving etch uniformity in reticle etching by eliminating local effects at the edge of the reticle is disclosed. The present invention relates to a reticle frame which surrounds the reticle. The reticle frames are patterned with a pattern profile similar to that of the reticle to prevent edge uniformities of the reticle by allowing uniform plasma etching of the entire reticle surface. The reticle frames may also be used to move the reticle in and out of etch chambers without damaging them.

Use of a chemically active reticle carrier for photomask etching

Methods of forming contact openings and methods of controlling the degree of taper of contact openings are described. In one implementation, a layer is first etched through a contact mask opening using a first set of etching conditions. The etching conditions provide a first degree of sidewall taper from vertical, if etching completely through the layer. After the first etching, the layer is second etched through the contact mask opening using a second set of etching conditions. The second set of etching conditions provide a second degree of sidewall taper from vertical, if etching completely through the layer. The second degree of sidewall taper is different from the first degree of taper. In another embodiment, a material through which a contact opening is to be etched to a selected depth is formed over a substrate. A masking layer having an opening therein is formed over the material. The material is first etched through the opening with the first etch having a first selectivity relative to the masking layer. After the first etch, and at a depth which is less than about 50% of the selected depth, the material is second etched, with the second etch having a second selectivity relative. to the masking layer which is greater than the first selectivity. In a preferred implementation, the second degree of selectivity is achieved by modifying an etch parameter during the etching of the contact opening.

Methods of forming openings and methods of controlling the degree of taper of openings

In but one aspect of the invention, a plasma etching method includes forming polymer material over at least some internal surfaces of a dual powered plasma etch chamber while first plasma etching an outer surface of a semiconductor wafer received by a wafer holder within the chamber. After the first plasma etching, second plasma etching is conducted of polymer material from the chamber internal surfaces while providing a bias power at the wafer holder effective to produce an ac peak voltage at the wafer surface of greater than zero and less than 200 Volts. In one implementation, second plasma etching is conducted of polymer material from the chamber internal surfaces while providing a bias power at the wafer holder of greater than zero Watts and less or equal to about 1 Watt/cm,of wafer surface area on one side.

Methods of forming contact openings and methods of controlling the degree of taper of contact openings are described. In one implementation, a layer is first etched through a contact mask opening using a first set of etching conditions. The etching conditions provide a first degree of sidewall taper from vertical, if etching completely through the layer. After the first etching, the layer is second etched through the contact mask opening using a second set of etching conditions. The second set of etching conditions provide a second degree of sidewall taper from vertical, if etching completely through the layer. The second degree of sidewall taper is different from the first degree of taper. In another embodiment, a material through which a contact opening is to be etched to a selected depth is formed over a substrate. A masking layer having an opening therein is formed over the material. The material is first etched through the opening with the first etch having a first selectivity relative to the masking layer. After the first etch, and at a depth which is less than about 50% of the selected depth, the material is second etched, with the second etch having a second selectivity relative to the masking layer which is greater than the first selectivity. In a preferred implementation, the second degree of selectivity is achieved by modifying an etch parameter during the etching of the contact opening.

Growing community of inventors

Boise, ID, United States of America

Richard L Stocks