Fujitsu Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Agilent Technologies, Inc.

Other

Nvidia Corporation

Palau Acquisition Corporation (delaware)

Avago Technologies General IP Pte, Ltd.

Richard L Schober, Jr

Raghu Sastry

Ian G Colloff

Rick Reeve

Hirotaka Tamura

Thomas M Wicki

Yoichi Koyanagi

Jeffrey D Larson

Albert Mu

Mercedes E Gil

Eric Lyell Hill

Prasad Vajjhala

Hungse Cha

John R Slice

Patrick James Helland

Damon W Finney

Marc A Schaub

Yolin Lih

Norman C Chou

Edmundo Rojas

Kohtaro Gotoh

Dev Datta

Zhang Xiaoyang

Varaprasad Vajjhala

Mohamed Magdy Talaat

Ashwin S Subramanian

Albert C Kuo

Paul S Serris

Embodiments relate to an image signal processor that includes an image processing circuit, a buffer, and a rate limiter circuit. The image processing circuit perform operations associated with image signal processing. The buffer stores the image data provided by the system memory. The buffer includes a shared that is dynamically allocated among the image processing circuits. The rate limiter circuit arbitrates allocation of the shared section. The arbitration process includes allocating data credits for the shared section to an image processing circuit. The rate limiter circuit determines a first number of blocks in the shared section that are allocated for pending requests and a second number of blocks that include data pending to be consumed by the image processing circuit. If the total allocated blocks occupied by the image processing circuit exceed a throttling threshold, the image processing circuit will be throttled by an exponential factor.

Shared dynamic buffer in image signal processor

Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.

Cyclic redundancy check generation via distributed time multiplexed linear feedback shift registers

The present invention discloses a digital self-timed timer for measuring the passage of time; a digital self-timed pulse generator for generating both continuous and finite pulse sequences; and a digital self-timed data receiver for recovering data from an asynchronous, two-wire bit-channel. Being self-timed, a disclosed self-timed timer measures time as a function of logic delays incurred while executing a sequence of internal state transitions. A pulse generator supports both a triggered pulse mode and continuous clock generation; pulse widths and pulse intervals are programmable. A data receiver may recover a data bit from each received two-bit code word and outputs recovered data and an associated write strobe for each recovered datum.

Self-timed timer

A method and system of communicating data between a source interconnect device and a destination interconnect device are defined. The method includes adding an identification component to the data at the source interconnect device prior to communicating the data, and extracting the identification component at the destination interconnect device. The identification component is then processed at the destination interconnect device, the identification component relating to the contents of the data. The invention extends to a machine-readable medium embodying a set of instructions for executing the method and to an interconnect device.

Method and system to control the communication of data between a plurality of interconnect devices

A pointer manager is described. The pointer manager includes write circuitry to enter, into a queue that is implemented with a first memory, a pointer value that a read hub has exhausted the use of. The pointer manager also includes read circuitry to remove, from said queue, a pointer value that is to be sent to a write hub. The pointer manager also includes write circuitry to add, to a link list that is maintained with a second memory, a pointer value that is to be sent to the write hub. The pointer manager also includes read circuitry to obtain, from said link list, a pointer value that is to be sent to a read hub.

Apparatus and methodology for a pointer manager

A scheduler to manage the reading activity of a plurality of read hubs is described. Each read hub is capable of reading a piece of a packet from a different memory bank within a same cycle of operation so that pieces of different packets can be read from the memory banks within the same cycle of operation. The scheduler: 1) defines each read hub as an active read hub or inactive read hub, wherein an active read hub is engaged to read at least one packet from the memory banks and an inactive read hub is not so engaged; 2) defines each active read hub as a low speed mode read hub or a high speed mode read hub, wherein, a first packet read by a high speed mode read hub is read from the memory banks at a faster rate than a second packet read by a low speed mode read hub; and, 3) dynamically changes the number of active read hubs, the number of low speed mode read hubs and the number of high speed mode read hubs in light of traffic conditions.

Apparatus and methodology for an input port scheduler

A method to manage resource requests within an arbiter associated with an interconnect device includes identifying a first resource, required to issue a grant responsive to a resource request. If the first resource is unavailable, the resource request is placed within a first queue associated with the first resource. The first queue is a queue within a first group of queues for a first resource type of the first resource. A second group of queues is maintained for a second resource type.

Method and system to manage resource requests utilizing link-list queues within an arbiter associated with an interconnect device

A networking system includes a plurality of ports, each adapted to send and receive data. A switch core has a first channel configured to receive a logical input flow from each of the plurality of input ports, and has a second channel configured to receive a raw input flow from each of the plurality of input ports. Each logical input flow is carried by its corresponding raw input flow. A plurality of port mirrors are selectable from the plurality of ports. Each of the plurality of port mirrors is configured to produce a duplicate copy of at least one of the logical input flow and the raw input flow available at a selected port.

Method and apparatus for input/output port mirroring for networking system bring-up and debug

A method and apparatus to allocate resource capacity within an interconnect device in accordance with a resource allocation table (e.g., a priority list) facilitate identification of a resource consumer to be allocated a portion of the resource capacity in an efficient manner. The resource allocation table stores a number of allocation entries indicating an allocation of the resource capacity to a number of resource consumers (e.g., virtual lanes). A ranking vector corresponding to a first allocation entry within the allocation table is retrieved. A pending request vector, indicating for which of the plurality of resource consumers a resource request is pending, is generated. A selected resource consumer to consume at least a portion of the resource capacity is selected, the selection being performed utilizing the ranking vector and the pending request vector. The ranking vector is derived from the resource allocation table and comprises a list of resource consumers of the plurality of resource consumers, the list being ordered in accordance to an order of appearance of a first allocation entry for a respective resource consumer within the resource allocation table.

Method and system to allocate resources within an interconnect device according to a resource allocation table

A write hub is described. The write hub has a plurality of registers. Each one of the registers helps generate a write address to a different memory bank from amongst a plurality of memory banks. Each of the registers are arranged in a ring so that each register can pass a pointer value toward a next register within the ring. The ring of registers further comprise a multiplexer between each of the registers. Each multiplexer has an output path that flows toward a next register within the ring relative to the multiplexer. Each multiplexer can introduce a pointer value to the ring at a next register within the ring.

Apparatus and methodology for a write hub that supports high speed and low speed data rates

A method and system are described to compute a status for a circular queue within a memory device. A head pointer and a tail pointer are maintained to identify a head entry and a tail entry, respectively, within the queue. In response to an updating of at least one of the head pointer and the tail pointer, at least one of a near-full or a near-empty condition is detected. The detection is performed utilizing parallel operations. The detection of the near-empty and/or near-full conditions may be useful to avoid underflow and overflow errors.

Method and system to compute a status for a circular queue within a memory device

A method to process a multicast transfer request within an interconnect device includes receiving the multicast transfer request pertaining to a packet stored by the interconnect device. A number of unicast transfer requests are spawned based on the multicast transfer request. Responsive to a generation of a transfer grant for at least one of the number of unicast transfer requests, a determination is made whether transfer grants have been generated for all of the number of unicast transfer requests. If so, then the packet stored by the interconnect device, and to which the multicast transfer request pertains, is discarded.

Method and system to process a multicast request pertaining to a packet received at an interconnect device

A method for detecting a timeout condition for a data item (e.g., a request) within the process (e.g., within an arbitration process) includes maintaining a current time as a first N-bit binary number (A). An event time of an occurrence of an event pertaining to the data item within the process is recorded and stored as a second N-bit binary number (B). A predetermined time limit, expressed as a non-negative integer K, is configured. K is less than N and K is a logarithm base 2 of the predetermined time limit. A timeout condition pertaining to the data item is detected when a difference between the current time and the event time exceeds the predetermined time limit. The detection of the timeout condition is performed utilizing a single-stage operation. This single stage operation may include computing A (current time)&#x2212;B (event time) modulo 2&#x2267;2.

Method and apparatus to detect a timeout condition for a data item within a process

According to a first aspect of the present invention, there is provided a method to receive a request from one of a plurality of pipelines to read a data record from a memory location within a first copy of a table. The method also includes a determination that there was a request to read the same memory location within a previous cycle. The method further includes the retrieval of a current version of the data record requested.

Growing community of inventors

Cupertino, CA, United States of America

Richard L Schober, Jr