Compaq Computer Corporation, Inc.

Richard L Pyra

Mark W Welker

Thomas M Albers

John V Eberst

Darwin Fontenot

Jack E Bresenham

Paul B Wood

Wood, Paul B

A graphics processor uses a line draw facility to receive first and second values indicative of the coordinates of respective first and second end points of a line. The reception of the second value is sensed by the line draw facility and line data is generated responsive to the sensing of the second value.

Video graphics controller with high speed line draw processor

A graphics device includes first and second endpoint memories where coordinates of a line can be stored. State logic within the graphics device calculates line parameters from the first and second endpoints. The calculated line parameters include a line error term which can be stored in an error term memory. The error term memory is writeable from a source external to the graphics device, such as the CPU of a computer system, so that the external source can modify the contents of the error term register.

Video graphics controller with improved calculation capabilities

Video graphics controller with automatic starting for line draws

Line draw circuitry receives parameters defining first and second endpoints of a line and calculates line parameters based on the first and second endpoints. The line parameters are then stored in a memory. A 'calculate-only' control signals determines whether a line is drawn immediately after calculation (and storing) of the end parameters or whether the line is drawn responsive to a subsequent 'start' signal. If the line is to be drawn responsive to the start signal, the line parameters may be modified prior to drawing the line.

Circuitry for drawing lines includes a video memory for storing pixel data and circuitry for generating a sequence of addresses defining a line of pixels in the video memory. A first memory stores a sequence of pattern units corresponding to the generated sequence of addresses. A second memory stores a value indicating a current pattern unit. Writing circuitry writes to the video memory at a generated address responsive to a current pattern unit. A third memory stores a control value which is accessed by update circuitry for updating the second memory to indicate the next pattern unit. The update circuitry may selectively update the second memory to the sequential pattern unit or reset the second memory to a predetermined pattern unit.

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Houston, TX, United States of America

Richard L Pyra