International Business Machines Corporation

Kabushiki Kaisha Toshiba

Siemens Aktiengesellschaft

Other

Richard L Kleinhenz

Wesley Charles Natzle

Chienfan Yu

Jack Allan Mandelman

Stanley Everett Schuster

Badih El-Kareh

Carl John Radens

Herbert Lei Ho

Laertis Economikos

Tze-Chiang Chen

Gary Bela Bronner

Harold John Hovel

Hiroyuki Akatsu

Heinz Hoenigschmid

Soichi Nadahara

Matthias Ilg

Ronald Wayne Nunes

Justin W Wong

Radhika Srinivasan

Junichiro Iba

Karl Paul Muller

Brian Christopher Barker

Gary R Moore

Klaus B Roithner

Mark L Reath

Horst Zisgen

Edward P Higgins

Marlene Isabel Almonte

Shigeki Sugimoto

Klaus Roithner

Klaus Penner

Masakatsu Tuschiaki

A solution for managing a manufacturing environment using operating data for each of a plurality of tools in the manufacturing environment. The operating data can include actual resource consumption data and/or actual exhaust generation data for a tool while the tool implements at least a portion of a recipe to manufacture one of a plurality of types of products manufactured in the manufacturing environment. Operation of the manufacturing environment can be configured to optimize one or more aspects of resource consumption and/or exhaust generation during the manufacture of desired quantities of the plurality of types of products within a desired time frame using the operating data.

Manufacturing management using tool operating data

An electrical method is described for determining the presence of certain defects in the buried oxide of silicon-on-insulator wafers which cause electrical breakdown at voltages low enough to cause failure during circuit processing. The method consists of carrying out current-voltage measurements on gold/silicon/buried oxide/substrate devices isolated by selective etching and analyzing the current-voltage behavior in terms of short circuit defect densities, low voltage breakdown defects, and excess current leakage defects. An additional method for detecting the low voltage breakdown defects is to monitor light flashes which accompany the breakdown.

Electrical method for assessing yield-limiting asperities in silicon-on-insulator wafers

A shallow trench isolation structure for a semiconductor device and the method for manufacturing the shallow trench isolation device within a semiconductor substrate. The shallow trench isolation structure is divot-free and includes un-annealed dielectric material as the trench fill material. The intersection of the structure and the semiconductor surface in which it is formed, is free of silicon nitride, but the isolation structure may include a silicon nitride liner which is within the trench and recessed below the semiconductor surface.

Structure and method for producing low leakage isolation devices

Fabrication of trench capacitors using disposable hard mask

An integrated circuit and a method of manufacturing an integrated circuit comprises forming an insulator over a substrate, forming a trench in the insulator and the substrate, undercutting the insulator to form a gate conductor opening between the substrate and the insulator adjacent the trench, and forming a gate oxide and gate conductor in the gate conductor opening.

Self-aligned deep trench DRAM array device

A method of forming a buried plate electrode for a trench capacitor of a semiconductor memory device is provided. Trenches are formed in a semiconductor substrate and a dopant source film is formed on the sidewalls and bottom walls of the trenches. A resist is formed on the dopant source film which fills in the trenches. The resist is recessed to remain in the trenches at a level which is below the surface of the semiconductor substrate. Impurities are implanted into the semiconductor substrate using the recessed resist as a block mask. The dopant source film is etched using the recessed resist as an etching mask and the recessed resist is then removed. The implanted impurities and dopants from the dopant source film are diffused into the semiconductor substrate to form a buried plate electrode.

Method of making a semiconductor memory device having a buried plate

Hydrogen fluoride undercut of oxide layers may be reduced by using a low pressure mixture of gaseous hydrogen fluoride and gaseous ammonia mixture. Organic photoresists can be used as a masking material when using the gaseous hydrogen fluoride/ammonia mixture without resulting in an enhanced reaction rate. In addition, because of the reaction conditions, the dimensions in the oxide layer being etched can be specifically sized smaller than openings made in the overcoating masking material.

Vapor phase etching of oxide masked by resist or masking material

A method of patterning a layer on sidewalls of a trench in a substrate for integrated circuits includes the steps of forming an insulator layer on sidewalls of a trench in a substrate with a horizontal top surface above the sidewalls, recessing a masking material such as an organic photoresist in the trench below the top surface of the substrate such that a portion of the insulator layer on the sidewalls of the substrate is exposed, and etching the insulator layer with a gaseous hydrogen flouride-ammonia mixture. The masking material and the substrate are composed of a different material than the insulator layer.

Method of patterning sidewalls of a trench in integrated circuit

An optimized trench capacitor structure which is useful as a decoupling capacitor or a storage capacitor can be manufactured without added process complexity. As an on-chip decoupling trench capacitor structure, the structure reduces the series resistance to outer and inner plates and results in an acceptable RC delay, while maintaining a high capacitance per unit area. As a storage capacitor with a buried shield, the trench capacitor structure exhibits high immunity to alpha particle and cosmic radiation induced failures. The trench capacitor structure which includes a buried n-well in a silicon substrate. A trench is formed in the substrate and extends through the buried n-well. A dielectric film is formed on an inner surface of the trench, and an inner plate formed as a polysilicon fill within the trench is connected to a surface n+ film formed during definition of peripheral source/drain contacts of the integrated circuit. An outer plate of the capacitor in the form of an out diffusion from the trench provides a low resistance electrical contact with the substrate. A number of these capacitors can be combined in a very efficient X-Y array of decoupling capacitors.

Trench capacitor structures

Reduced current consumption in a DRAM during standby mode is achieved by switching off the power source that is connected to, for example, the n-well.

Reduced stand by power consumption in a DRAM

Oxide layer patterned by vapor phase etching

Trench sidewall patterned by vapor phase etching

A method of forming a DRAM storage cell with a trench capacitor in an SOI substrate is taught. The method involves forming an field effect transistor (FET) consisting of a source, drain, channel regions in a device layer, a gate oxide layer on the surface of the device layer and a gate electrode over the channel region. The trench capacitor is formed by the following steps: 1) forming a masking layer over the device layer and patterning an opening corresponding to the trench in the masking layer, 2) anisotropically etching a first trench corresponding to the opening in the masking layer to a first depth, through the SC device layer and the buried oxide layer, extending slightly into the substrate body, 3) forming a diffusion barrier collar along the sides of the first trench to the first depth, 4) forming a second trench by anisotropically etching the substrate body exposed by the first trench to a second depth, so that the silicon of substrate body exposed by the second trench becomes a first electrode of the trench capacitor, 5) forming a node dielectric layer on surface of the substrate body exposed by the first trench, 6) forming a doped polysilicon plug in the first and second trench so as to form a second electrode of the trench capacitor, said plug further making contact to the drain region of the FET. A separate substrate contact to the substrate body is formed through the front or backside so as to contact to the first electrode of the capacitor. Oxide isolation regions between adjacent transistors are formed to complete the SOI-DRAM.

Method of making silicon on insulator buried plate trench capacitor

A capacitance storage trench for a DRAM cell includes a trench having at least one sidewall, a bottom wall and a plurality of rods extending away from the bottom wall. The at least one sidewall, the bottom wall and the rods are coated with a capacitive dielectric layer. A layer of semiconductive material is disposed over the dielectric layer. The plurality of rods expand the overall surface area of the trench and thus, provide a significant increase in capacitance storage of the storage trench. The capacitance storage trench is formed in a method which includes the steps of forming a plurality of buried oxygen precipitates in a selected region of a substrate and using the oxygen precipitates as micromasks during a conventional trench etch process.

Enhanced deep trench storage node capacitance for DRAM

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Wappingers Falls, NY, United States of America

Richard L Kleinhenz