Cypress Semiconductor Corporation

Richard L Kapusta

Caleb Chan

Christopher W Jones

Haneef D Mohammed

Jeffery Mark Marshall

A programmable logic device includes a plurality of clusters of logic elements. Each of the clusters may include a respective programmable interconnect matrix with each of the logic blocks of each cluster being coupled to the respective programmable interconnect matrix of the cluster. Each of the clusters may be symmetrically coupled to a row and a column of a global routing matrix. The row and the column of the global routing matrix may themselves be symmetrical and each row and/or column may be coupled to an input/output cell of the programmable logic device. The global routing matrix may comprise a plurality of programmable interconnections. In a further embodiment, a symmetrical input/output scheme for a programmable logic device may include a first level routing architecture configured to provide limited intercommunication between a first cluster of logic blocks and a second cluster of logic blocks and a second level routing architecture configured to provide intercommunication between logic blocks within the first cluster. The second level routing architecture being symmetrically coupled to the first level routing architecture at two points of the first cluster. The symmetrical input/output scheme may have the second level routing architecture coupled to the first level routing architecture through a programmable interconnect matrix. The first level routing architecture may further comprise a non-segmented routing matrix which may be symmetrical and which may be laid out as a row and column routing matrix.

Symmetric logic block input/output scheme

A scalable routing architecture for high density programmable logic devices involves the utilization of a two-dimensional network of non-segmented routing channels to serve as global interconnects between clusters of logic blocks. Each cluster of logic blocks is a CPLD-like structure which includes a number of logic blocks connected together by a local interconnect. Logic signals that need to enter a cluster, either from an I/O pin or from another logic block of another cluster, do so by traversing from those sources though a channel interconnect. Similarly, logic signals produced by a cluster can be routed to an I/O pin or to another logic block of another cluster across one of the channels. A switch matrix is implemented at intersections between the channels to allow logic signals to be transferred between rows and columns of the channels.

Hybrid routing architecture for high density complex programmable logic devices

A circular product term allocator configured to provide connections for product term signals to macrocells of a programmable logic device is provided. The circular product term allocator may provide such connections through a logic OR function. Alternatively, a homogeneous product term allocator may be configured to provide connections for product term signals to macrocells of a programmable logic device. The homogeneous product term allocator may be configured to provide each of the product term signals to an equal number of macrocells. In yet another embodiment, a programmable logic device includes a plurality of macrocells and a product term allocator configured to provide an equal number of product term signals to each of the macrocells. In yet a further embodiment, a method of distributing product terms in a programmable logic device is accomplished by configuring a product term allocator to provide an equal number of product terms, but fewer than all of the product terms, to each of the macrocells.

Circular product term allocations scheme for a programmable device

The macrocell is configured to allow a single register to be employed either as a register for storing internal macrocell product terms (or logical combinatorial thereof) or as an input register for directly storing signals received from an input/output pin. One embodiment of the macrocell, described herein, includes the register and the input/output pin, along with three two-to-one multiplexers and an output enable logic unit. Feedback lines are also provided. The components are interconnected and appropriate multiplexer and output enable selection signals are provided to allow the macrocell to input and output a variety of combinations of signals including combinatorial and registered logic signals, buried combinatorial and buried registered logic signals, and input and output signals. In one exemplary mode, the macrocell is controlled to store an input signal in the register with the output signal of this register routed to one of the feedback lines while also providing a buried combinatorial feedback path from the macrocell logic line input onto another of the feedback lines. Contents of the register may be output from the macrocell to the input/output pin or fedback along one of the feedback lines to other components of a device containing the macrocell such as a programmable interconnect matrix of a complex programmable logic device. Method and apparatus embodiments of the invention are provided.

Macrocell having a dual purpose input register for use in a logic device

A complex programmable logic device (CPLD) is disclosed which includes a set of logic blocks each containing a product term array and a set of macrocells. A clocking arrangement is provided which allows selection between synchronous and asynchronous clock signals for input to each macrocell. The clocking arrangement is hierarchical. More specifically, a synchronous clock multiplexer is provided, within each logic block, for reducing an input set of N synchronous clock signals, and their complements, to a reduced set of M synchronous clock signals. The selected synchronous clock signals, and J product term asynchronous clock signals, or their complements, provided by the corresponding product term array, are routed into each of the macrocells of the logic block. An additional multiplexer is provided within each macrocell for selecting one clock signal from among the M synchronous clock signals and the J product term signals. The hierarchical clocking arrangement provides considerable flexibility for selecting clocking signals, both on a block by block basis, and on a macrocell by macrocell basis yet requires relatively modest chip resources for implementation. A specific example is described herein where in N is six, M is three and J is one.

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San Jose, CA, United States of America

Richard L Kapusta