Microchip Technology Inc.

Richard L Hull

Randy L Yach

Gregory C Bingham

Scott Raymond Fink

Scott Ellison

Sean Steedman

Zacharias Marthinus Smit

Ryan Scott Ellison

Ruan Lourens

Gabriel Rosca

Vivien Neil Delport

Jerrold S Zdenek

John Charais

Paul H Hofhine

Eric Schroeder

Razvan Enachescu

Michael Charles

Stephen C Hinkle

James Clark Rogers

Alexandru Vidrasan

Voltaire Ganchorre

One or more embodiments relate, generally, to microcontroller input/output (I/O) and limiting or disabling static current draw at general purpose inputs, including during low power situations where a voltage input may be lower than a supply voltage. In some embodiments, a general purpose input may include selectable input buffers and logic that is configured to selectively enable an input buffer associated with a voltage domain substantially the same as an input voltage of the general purpose input, and selectively disable the other input buffers.

Selectable input buffers of general purpose inputs and microcontrollers having the same

A circuit for providing back-up power includes a switching circuit configured to be coupled to a first power source and a second power source. The circuit includes a domain voltage level monitor circuit coupled with the first power source and the second power source and with output of the switching circuit. The circuit includes a dynamic level shifter circuit coupled with the first power source and the second power source and an output of the domain voltage level monitor. The circuit includes a double controlled latch circuit coupled with the first power source and the second power source and an output of the dynamic level shifter circuit. The double controlled latch circuit is configured to provide control signals to the switching circuit.

Seamless switching control for low power battery backup system

A mains voltage zero-crossing detector has a constant voltage forced on an external node by driving transistor devices with appropriate control signals provided by a feedback loop around a highly power efficient class B configuration comprising an operational amplifier having single ended dual outputs and a class B control circuit. Mains power zero crossings may then be detected by monitoring the drive current of devices driven by this amplifier. Wherein Class B control and current mode detection provide accurate detection of the driven signal without depending on any voltage threshold that may depend on temperature, process fabrication and/or supply voltage.

Mains voltage zero-crossing detector

An integrated circuit device provides a choice of external pins (connections) that may be user selectable for coupling an external filter/stabilization capacitor to an internal voltage regulator. However, connecting the output of a internal voltage regulator to an uncharged external filter/stabilization capacitor (or to a capacitor charged to a different voltage level than the internal regulation voltage) through a low impedance path can cause the regulator output voltage to sag/spike if the internal voltage regulator tries to charge/discharge the capacitor up/down to equilibrium with the regulator output voltage. To minimize this potential sag/spike, the voltage on the external filter/stabilization capacitor may be adjusted in a controlled manner to substantially the same voltage as the voltage on the output of the internal voltage regulator, and then the internal voltage regulator is operationally coupled through a low impedance to the external regulator filter/stabilization capacitor.

Connection of an internal regulator to an external filter/stabilization capacitor through a selectable external connection and prevention of a current surge therebetween

A brown-out-reset circuit having programmable power and response time characteristics. These characteristics may be programmed over an n-bit wide bus for 2different characteristics ranging from very low power consumption and slower response time to very fast response time and higher power consumption. A serial one wire bus may be used instead of the n-bit wide bus.

Variable power and response time brown-out-reset circuit

An Integrated Circuit (IC) package is disclosed comprising an IC chip with a microcontroller therein having an n-bit data bus, and up to n pins electrically coupled to the microcontroller. The IC package also includes a control register coupled to the microcontroller for receiving enable and disable signals from the microcontroller. One or more of the pins have one or more functional block associated thereto. Each functional block defines a specified function for its corresponding pin. Thus, each pin having a plurality of corresponding functional blocks has a number of potential functions equal to the number of corresponding functional blocks. The specific function for a given pin is selected by the enable signal from the control register which selects the appropriate functional block upon appropriate command from the microcontroller. By using pins with multiple functions, the instant invention permits an n-bit architecture microcontroller to use less than or equal to n pins.

Integrated circuit (IC) package with a microcontroller having an n-bit bus and up to n-pins coupled to the microcontroller

An Integrated Circuit (IC) package is disclosed comprising an IC chip with a microcontroller therein having an n-bit data bus, and up to n pins electrically coupled to the microcontroller. The IC package also includes a control register coupled to the microcontroller for receiving enable and disable signals from the microcontroller. One or more of the pins have one or more functional block associated thereto. Each functional block defines a specified function for its corresponding pin. Thus, each pin having a plurality of corresponding functional blocks has a number of potential functions equal to the number of corresponding functional blocks. The specific function for a given pin is selected by the enable signal from the control register which selects the appropriate functional block appropriate command from the microcontroller. By using pins with multiple functions, the instant invention permits an n-bit architecture microcontroller to use less than or equal to n pins.

A multipurpose input/output circuit providing full input output current drive capability and special mode selection on a single device pin. The circuit includes first and second high voltage detectors coupled to the pin, at least one pin bias circuit, and a mode selector. The mode selector determines whether the pin operates as either an input or output. One of the high voltage detectors detects a high voltage on the pin and causes the bias circuit to disconnect the pin from the supply voltage. The other high voltage detector operates to detect a special mode voltage on the pin and set the device into a special mode.

High voltage multipurpose input/output circuit

A free-running microcontroller (i.e., one without any reset signal) is shown with special mode enable detect logic for placing the microcontroller into the test or special operations mode, without the benefit of a dedicated pin for such purposes. Rather, the instant invention implements the methodology of first applying a test voltage to indicate to the free-running microcontroller that the test mode is to be entered. Since the device has no reset signal to interrupt normal operation once it has begun, the test voltage is applied before the power supply V.sub.DD to ensure that the device enters test mode before it can enter normal operation.

Microcontroller having special mode enable detection circuitry and a

An Integrated Circuit (IC) package is disclosed comprising an IC chip with a microcontroller therein having an n-bit data bus, and up to n pins electrically coupled to the microcontroller. The IC package also includes a control register coupled to the microcontroller for receiving enable and disable signals from the microcontroller. One or more of the pins have one or more functional block associated thereto. Each functional block defines a specified function for its corresponding pin. Thus, each pin having a plurality of corresponding functional blocks has a number of potential functions equal to the number of corresponding functional blocks. The specific function for a given pin is selected by the enable signal from the control register which selects the appropriate functional block upon appropriate command from the microcontroller. BY using pins with multiple functions, the instant invention permits an n-bit architecture microcontroller to use less than or equal to n pins.

Microcontroller having an n-bit data bus width with less than n I/O pins

A self timed precharge sense amplifier for allowing high speed reading of a memory cell of a memory array. The self timed precharge sense amplifier uses a precharge device for generating an output voltage which is used to ramp up a voltage level of a column of the memory array where the memory cell is located. State control circuitry is coupled to the precharge device for activating and deactivating the precharge device. A sense amplifier is coupled to the precharge device and to the state control circuitry for monitoring the output voltage of the precharge device and for signalling the state control circuitry to deactivate the precharge device when the output voltage has reached a threshold voltage level set by the sense amplifier which is a minimum amount of voltage required to properly read the memory cell.

Self timed precharge sense amplifier for a memory array

A voltage regulator which will clamp the row voltage of a memory cell or array. The voltage regulator will clamp to a value which is greater than the erased threshold voltage of the memory cell and less than the worst case programmed threshold voltage of the memory cell. The voltage regulator uses an unprogrammed memory cell of the memory array for allowing the row voltage outputted by the voltage regulator to be self-tracking over manufacturing process variations and ambient environmental influences. A switching circuit is coupled to the unprogrammed memory cell for clamping the row voltage outputted by said voltage regulator below the programmed threshold voltage level.

Voltage regulator for clamping a row voltage of a memory cell

A technique for reading data from a selected memory element of an EPROM array having rows and columns with addressable memory elements which may be selectively accessed at respective intersections of the rows and columns. Each memory element includes a transistor having gate, source and drain electrodes, and after selection of a particular memory element from which data is to be read by appropriately biasing the row and column associated with that memory element, the source electrode thereof is selectively connected to ground by a switching element to allow current flow through the source-drain path of the memory element and enable the readout of data therefrom after the drain and gate voltages of the memory element have stabilized.

Switched ground read for EPROM memory array

A technique is disclosed for reading a memory element of an EPROM array embedded in a microcontroller chip which has been scaled down from a previous design by virtue of reduced line widths of a process technology used for fabricating the chip. The microcontroller chip has a predetermined supply voltage, and the array comprises rows and columns of addressable memory elements which may be selectively accessed to read data content therefrom in a low voltage mode in which the supply voltage initially rises and ultimately reaches substantially its maximum voltage during a read cycle. A regulated reference voltage is used to exercise row and column control in the low voltage read mode by tracking the level of the supply voltage up to a certain preselected level below the maximum supply voltage, and by clamping the row and column control voltage at substantially the preselected level despite increases in the level of the supply voltage above the preselected level.

Voltage reference generator for EPROM memory array

A microcontroller circuit having firmware selectable oscillator trimming includes, in combination, a microcontroller, an oscillator located within the microcontroller for providing a system clock signal for the microcontroller, and a memory portion for providing trimming data to the oscillator for trimming frequency of the system clock. The microcontroller circuit includes microcontroller logic which has the trimming data stored therein for transfer to the memory portion. Additionally, the microcontroller logic permits the user to alter the trimming data after it has been transferred to the memory portion, thereby permitting the user to alter the amount of modification of the system clock frequency from the amount associated with the trimming data.

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Chandler, AZ, United States of America

Richard L Hull