Tandem Computers Incorporated

Applied Micro Circuits Corporation

Scientronix Inc.

Summit Data Systems LLC

Richard L Harris

Robert W Horst

Paul Roger Stonelake

Christophe Therene

Alex Ga Hing Tang

Jack A Wiens

Mizanur Mohammed Rahman

Peter Nobel

Joseph Fraser

Heiki Kask

A disk array controller detects disk drive power-on-reset events that may cause a disk drive to lose uncommitted write data stored in its cache. When an unexpected disk drive power-on-reset event is detected, the disk array controller may initiate an appropriate corrective action. For example, the disk array controller may initiate a disk drive rebuild operation, or may re-send a set of write commands to the disk drive.

Disk array controller capable of detecting and correcting for unexpected disk drive power-on-reset events

A disk array controller reliably detects disk drive power-on-reset events that may cause a disk drive that has uncommitted write data stored in its cache to lose such data. The methods for detecting the power-on-reset events include operating the disk drives in an ATA security mode in which a power-on-reset of a disk drive will cause the drive to enter a locked state in which data transfer commands are aborted; and tracking power cycle count attributes of the disk drives over time. When a disk drive power-on-reset event is detected, the disk array may be efficiently restored to an operational state by re-executing or 'replaying' a set of write commands that are cached within the disk array controller. The invention is also applicable to single-disk-drive storage systems.

Storage system with disk drive power-on-reset detection

A disk array controller reliably detects disk drive power-on-reset events that may cause a disk drive that has uncommitted write data stored in its cache to lose such data. The methods for detecting the power-on-reset events include operating the disk drives in an ATA security mode in which a power-on-reset of a disk drive will cause the drive to enter a locked state in which data transfer commands are aborted; and tracking power cycle count attributes of the disk drives over time. When a disk drive power-on-reset event is detected, the disk array may be efficiently maintained in an operational state by re-executing or 'replaying' a set of write commands that are cached within the disk array controller. The invention is also applicable to single-disk-drive storage systems.

Storage system with disk drive power-on-reset detection and recovery

A system and process for generating a control program for execution by a programmable logic control unit including the steps of: providing a variable editing user interface allowing a user to define and edit variables including input variables and output variables; providing a program level editing user interface allowing the user to edit a program level; providing a state editing user interface allowing a user to define and edit a plurality of states of the control program; providing a condition editing user interface allowing a user to define and edit at least one condition for each of the states of the control program; and generating the control program as a function of associative relationships of the variables, states, and conditions.

System and method for programming a logic control unit

A process is provided for generating a flow chart representing a control program defined by associative relationships between program levels, states and conditions, each condition specifying a transition from an associated one of the states as a source state to a corresponding selected destination state upon satisfaction of the condition during execution of the control program by the logic control unit. Each program level defines a sub-process of the control program. The process includes the steps of rendering on a chart: a first group of state indicators each representing a corresponding one of a first plurality of the states, and including an associated first state anchor point; a first group of condition indicators each being associated with a corresponding one of the first group of state indicators, each of the first group of condition indicators indicating a corresponding one of a first plurality of the conditions, and including an associated first condition anchor point; a second group of state indicators each indicating a corresponding one of a second plurality of the states, and including an associated second state anchor point; a second group of condition indicators each being associated with a corresponding one of the second group of state indicators, each of the second group of condition indicators indicating a corresponding one of a second plurality of the conditions, and including an associated second condition anchor point; and for each of the conditions, a corresponding transition indicator indicative of transition information specified by the condition.

Process for generating program listings for programming a logic control

First and second banks of control stores are used to store microinstructions. Each bank contains three control stores: A horizontal control store, a vertical control store, and a jump control store. The horizontal control store contains the rank four microcode; the vertical control store contains the rank three microcode; and the jump control store contains the same microcode as the vertical control store but is used on conditional jump microoperations. This allows simultaneous accessing of different microinstructions using a single address incrementer. The control store banks are accessed in an overlapping manner so that upon each clock cycle one bank is loading the rank 3 and rank 4 registers. The sequencer according to the present invention includes a return address stack for returning from subroutine calls and trap routines. When processing trap routines, the return address stack stores two microinstruction addresses to allow processing of a previously encountered jump or call operation that may have been aborted when the trap routine was entered.

Microinstruction sequencer having multiple control stores for loading

Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and return to a desired line after a delayed call.

Enhanced CPU return address stack

Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored and return to a desired line after a delayed call.

Enhanced CPU microbranching architecture

An entry control store in a central processing unit (CPU) is addressed by the next macroinstruction to be executed by the CPU and fetches the microcode for the first line of that macroinstruction. Subsequent lines of microcode for that macroinstruction are fetched from a main control store.

Entry control store for enhanced CPU pipeline performance

Hardware for performing microcode branching in a pipeline central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit lines of microcode which are in the pipeline when a branch has been sensed. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupling loading and pushing to accommodate the two branching speeds. The microcode can specify loading the return address stack with a literal or register value to allow vectored branching and return to a desired line after a delayed call.

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San Jose, CA, United States of America

Richard L Harris