Texas Instruments Corporation

Richard L Guldi

Keith W Melcher

Frank D Poag

Douglas E Paradis

Chris D Atkinson

Deepak Arabagatte Ramappa

Basab Chatterjee

Yaojian Leng

Kenneth G Vickers

Randolph William Kahn

Robert F Kunesh

Edward J Leonard

Howard L Tigelaar

John P Williston

Vikram N Doshi

David R Wyke

Sima Salamati-Saradh

Hilario T Trevino

William D Light

Shangting Detweiler

James F Garvin, Jr

Jeffrey W Ritchison

Jimmie Brooks

Virgil Q Turner

Moitreyee Mukerjee-Roy

Mark R Visokay

Freidoon Mehrad

Wei-Yung Hsu

Yaw S Obeng

Kelly Jay Taylor

Satyavolu Srinivas Papa Rao

Asad Mahmood Haider

Toan Tran

Jae Hong Park

Kueing-Long Chen

Kalipatnam V Rao

James M Drumm

Satyavolu Papa Rao

Anand J Reddy

Sean M Collins

Robin D Worley

Roy D Clark

Kelly C Mollenkopf

Hiro Tomomatsu

Karanpreet Chahal

J Michael Grobelny

Paul C Hashim

William Pressnall

In accordance with the invention, there are semiconductor devices and methods of making semiconductor devices and holes. The method of making a semiconductor device can comprise forming a photoresist layer over a surface of a wafer, wherein the wafer comprises an edge that has a substantially rounded profile, an array of dies, and at least one edge die. The method can also comprise dividing a shot area into a plurality of shot portions and assigning a blind ID to each of the plurality of shot portions. The method can further comprise identifying one or more edge shot portions on the edge of the wafer for additional exposure; and exposing one or more times identified one or more edge shot portions on the edge of the wafer and blocking non-identified one or more non-edge shot portions.

By-die-exposure for patterning of holes in edge die

A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes.

Method to attain low defectivity fully silicided gates

Reducing chemical contaminants is increasingly important for maintaining competitive production costs during fabrication of electronic devices. There is currently no production floor capability for mapping chemical contaminants across an electronic device substrate on a routine basis. A scanning surface chemical analyzer for mapping the distributions of a variety of chemicals on substrates is disclosed. The analyzer includes an array of sensors, each of which detects a single chemical or narrow range of chemicals, a scanning mechanism to provide a mapping capability, an electrical signal analyzer to collect and analyze signals from the array of sensors and generate reports of chemical distributions, and an optical desorption mechanism to amplify detection. A preferred embodiment includes an array of miniature quadrupole mass spectrometers in the sensor array. Scanning modes include whole substrate mapping, region sampling, and spot sampling of known defect sites.

Close proximity scanning surface contamination analyzer

A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically isolated application and test circuits are formed thereon, directing an electron current inducing beam to the test circuit; measuring a current between the first and the second contact pads in the test circuit; determining an electron beam induced current (EBIC); and identifying one or more defect locations in the test circuit based on the EBIC and a location of the electron beam corresponding to the EBIC. A test circuit can include a plurality of semiconductor devices connected in parallel, a first contact pad coupled to a first terminal of the semiconductor devices, and at least a second contact pad coupled to a substrate terminal associated with the semiconductor devices.

Structures for testing and locating defects in integrated circuits

The invention provides a method of fabricating a semiconductive device []. In this embodiment, the method comprises depositing a hydrocarbon layer [] over a semiconductive substrate, forming an interconnect structure [] within the hydrocarbon layer [], and removing the hydrocarbon layer [] by sublimation.

Semiconductive device fabricated using subliming materials to form interlevel dielectrics

The present invention provides, in one embodiment, a method () of manufacturing a semiconductor device. A conventionally formed reticle is positioned over a resist located on a substrate (). A radiation path through the reticle and a window assembly located between a radiation source and resist (), is considered. It is determined whether or not the radiation would expose a predefined blocking area of the resist within the exposure zone (). If the radiation would expose a blocking area, then the window assembly is configured to prevent radiation from exposing the blocking area in the exposure zone (). Other embodiments include a window assembly () and system () to facilitate manufacturing of the semiconductor device according to the method ().

Adjustable lithography blocking device and method

A system and methods for the evaluation of the integrity of a wafer cassette and the disposition thereof are based upon evaluation of wafer measurement data obtained using a wafer sorter cassette mapping system utilized in-line during wafer sorting operations. In one embodiment, wafers are placed into slots in the wafer cassette. A wafer sorter cassette mapping sensor is scanned over the wafers in the wafer cassette. The positions of the wafers are measured while scanning the sensor over the wafers. The wafer position measurements are evaluated using a modeling system to determine slot positions, and a determination of the integrity of the cassette is generated. If the integrity determination indicates that the cassette is deformed beyond a predetermined value, the cassette is replaced. The measurement data may be stored in a data base for further trend analysis or for replacement forecasting.

Method and apparatus for cassette integrity testing using a wafer sorter

Speech or musical performance is electronically analyzed using DSP techniques and is compared to a stored text script or musical score, to enable display of and automated sequencing through multiple pages of the stored script or score. The performer can modify timing of sequencing if desired, for example dependent on performance speed or musical complexity. Automated highlighting or marking of measures or text assists the performer in keeping track of progress through the performance. During or after the performance, electronic comparison of the performance to the score or script provides feedback to the performer, highlighting differences between the actual performance and the desired performance as described by the score or script. Additional capabilities enhancing the learning process include digital recording and playback of the actual performance, and/or accompaniment by synthesis or playback of digital recording of other performance parts (for example, other instruments in an ensemble or other actors in a play).

Automatic page sequencing and other feedback action based on analysis of audio performance data

According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a photoresist layer on a surface of a wafer. The wafer includes an array of die that includes a plurality of complete die and at least one partial edge die. The wafer has an edge that has a substantially rounded profile causing undersized patterns in semiconductor devices formed on partial edge die. A first exposure intensity is assigned to a first group of die on the surface of the wafer. The first group of die includes a group of complete die, and the first exposure intensity is assigned based at least in part on the location of the first group of die on the surface of the wafer. A second exposure intensity is assigned to a second group of die on the surface of the wafer. The second group of die includes at least one partial edge die. The second exposure intensity less than the first exposure intensity to compensate for reduced line width due to the wafer edge topography. Energy is directed at the second group of die at the second exposure intensity to avoid over-exposure of the second group of die.

System and method for exposure of partial edge die

Semiconductor devices formed on wafers are inspected using a master wafer. A subject wafer of a semiconductor design is provided. The subject wafer has dies wherein semiconductor devices of the semiconductor design are formed and at a stage of fabrication. A current layer of the subject wafer is scanned to obtain a scanned layer/image. A master wafer comprising individual wafer/layer maps is obtained. The scanned layer is compared with a corresponding layer map. Matching and non-matching defects are identified from repetitive defects within the corresponding layer map and defects within the scanned layer. The matching defects are reviewed to classify and or identify causality. The master wafer is then updated.

Methods for detecting structure dependent process defects

An x-ray confocal defect detection system comprises an x-ray source, a confocal component, and defect detectors and operates on a target portion of a semiconductor device. The x-ray source generates x-ray energy. The semiconductor device includes a plurality of formed layers. The target portion is a selected layer or portion of the plurality of formed layers. At least a portion of the x-ray is transmitted through the semiconductor device as transmitted x-ray. The confocal component receives the transmitted x-ray and passes target x-ray intensity from the target portion of the transmitted x-ray energy. Detectors receive the target x-ray from the confocal component from which defect analysis can be performed.

X-ray confocal defect detection systems and methods

An alignment mark to be used in conjunction with e-beam imaging to identify specific feature locations on a chip including a unique 'L' shaped pattern of geometric features, which is easily detected by the recognition system of e-beam imaging equipment, and is located in close proximity to the specific circuit features under investigation at each level to be inspected. The requirements for an alignment mark design which is recognizable by state-of-the-art e-beam imaging systems are enumerated, as well as the methodology for application. The alignment marks which are included at each critical step add no cost to wafer processing, and any design cost is easily overcome by reduction in process development time by using defect learning.

Alignment mark for e-beam inspection of a semiconductor wafer

The present invention provides an electroplating process and a method for manufacturing an integrated circuit. The electroplating process includes, among other steps, placing a substratein an enclosurebeing substantially devoid of unwanted contaminants and forming a material layerover the substratewithin the enclosurethe enclosurestill being substantially devoid of the unwanted contaminants. The electroplating process further includes forming a thin layer of oxideover the material layerwithin the enclosure, the enclosurestill being substantially devoid of the unwanted contaminants during the forming the thin layer of oxide

Pretreatment for an electroplating process and an electroplating process in including the pretreatment

An in-situ particle monitor in an exhaust controls a particle sampler so that when a predetermined particle threshold is detected, the particle sampler is caused to gather samples from the exhaust in real-time. Electrical control signals are monitored to correlate variations in the signals with particle excursions for both analysis and sample collection triggering.

Method for intelligent sampling of particulates in exhaust lines

Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing order of the wafer lot. Positional data is captured for each wafer at both the send and receive ends of the process.

In-situ randomization and recording of wafer processing order at process tools

Growing community of inventors

Dallas, TX, United States of America

Richard L Guldi