Micron Technology Incorporated

Richard L Elliott

Guy F Hudson

Gurtej S Sandhu

Trung Tri Doan

John H Givens

Jody D Larsen

Michael A Walker

Christopher W Petz

Clement Jacob

A material deposition system comprises a dopant source containing at least one dopant precursor material, an inert gas source containing at least one noble gas, and a physical vapor deposition apparatus in selective fluid communication with the dopant source and the inert gas source. The physical vapor deposition apparatus comprises a housing structure, a target electrode, and a substrate holder. The housing structure is configured and positioned to receive at least one feed fluid stream comprising the at least one dopant precursor material and the at least one noble gas. The target electrode is within the housing structure and is in electrical communication with a signal generator. The substrate holder is within the housing structure and is spaced apart from the target electrode. A method of forming a microelectronic device, a microelectronic device, a memory device, and an electronic system are also described.

Material deposition systems, and related methods

A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposited upon the semiconductor wafer within the contact hole. A planarizing step isolates the first metal layer within the insulation layer in the form of a contact plug within the contact hole. A second metal layer is then deposited upon the semiconductor wafer over and upon the contact plug. Metallization lines are patterned and etched from the second metal layer. The contact hole may also be lined with a refractory metal nitride layer, with a refractory metal silicide interface being formed at the bottom of the contact hole as an interface between the contact plug and a silicon layer on the semiconductor substrate. Article qualities are achieved by the inventive method, including reduced interfacial resistance and its consequent faster signal speed for the structure, reduced metal creep where additional selected alloys are allowed to diffuse a selected quantity of preferred alloying elements from the first metal layer to the second metal layer, improved depth-of-focus requirements for patterning metallization lines, and resistance of electromigration in aluminum metallization lines.

Contact integration method

Contact integration article

The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a CMP process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chemical is a strong base chemical, like KOH, or potassium hydroxide. Moreover, the CMP process utilizes a system of closely regulating the timing of the two chemical processes. Specifically, during a first time period, both chemicals are applied; thus providing a given speed of the chemical removal of tungsten material. During a second time period, the KOH is removed, so as to slow down the chemical action and facilitate a greater degree of planarization.

IC mechanical planarization process incorporating two slurry

The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a cmp process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chemical is a strong base chemical, like KOH, or potassium hydroxide. Moreover, the cmp process utilizes a system of closely regulating the timing of the two chemical process. Specifically, during a first time period, both chemicals are applied; thus increasing speed of the chemical removal of tungsten material. During a second time period, the KOH is removed, thus slowing down the chemical action and importantly achieving a greater degree of planerization than is capable by the two chemical first time period.

A method is disclosed for improved side wall and bottom coverage of high aspect ratio space situated upon a substrate in two (2) steps. A lining is formed on a side wall surface of the space that terminated at a bottom surface. An opening then remains to a void defined by the lining and the bottom surface. The void is filled with a material passing through the opening to the space. When sputtered, the lining can be formed by a less-collimated sputtered particle flux, and the void can be filled by a collimated sputtered particle flux. The lining can be formed by flux in a plasma formed from a first gas having a neutral to ion ratio, and the void can be filled by a flux in a plasma formed from a second gas having a neutral to ion ratio lower than that of the first. Also, the lining can be formed by a flux in a plasma formed from a first gas having an atomic mass, and the void can be filled by a flux in a plasma formed from a second gas having an atomic mass lower than that of the first. The lining can be formed by sputtering a target having a crystal structure not preferentially oriented to maximize collimation thereof, and the void can be filled with a flux from a target having a crystal structure preferentially oriented to maximize collimation thereof. A confining magnetic field may be used to reduce electron losses at process chamber walls, allowing for improved collimation of the collimated flux. The substrate may also be heated or biased during exposure to the less-collimated flux to increase the good side wall and step coverage of the less-collimated flux, and cooled or reverse-biased during exposure to the collimated flux to increase the good bottom coverage of the collimated flux. Alternatively, the substrate may be exposed to only a collimated flux, but good side wall coverage can be achieved by alternating the temperature and/or bias of the substrate to provide the desired side wall and step coverage. Varied pressure can also be used to adjust material deposition.

Method for improved bottom and side wall coverage of high aspect ratio

A contact space filled with conductive material having good step coverage is disclosed. The contact space is formed in a dielectric layer with an upper surface. The contact space has sidewalls comprised of the dielectric layer and a bottom comprised of an underlying layer. The contact space is filled by first depositing a layer of an amorphous material such as TiAl.sub.3 over the bottom and sidewalls of the contact space, then filling the contact space with a metallic fill material such as an aluminum-containing fill material. The amorphous material is chosen particularly to have low reactivity with the metallic fill material, so that mobility of the metallic fill material over the surface upon which it is deposited is facilitated.

Trench/hole fill processes for semiconductor fabrication

The present invention is a polishing pad for use in chemical-mechanical planarization of semiconductor wafers by placing a wafer against a polishing surface of the polishing pad while rotating the polishing pad about its center in the presence of a polishing slurry. The polishing surface has formed therein one or more grooves extending in a spiral inwardly from the periphery to the center of the polishing pad. As a result, slurry is transported inwardly toward the center or toward the periphery of the polishing pad depending upon the circumferential direction of the spiral relative to the direction of rotation of the polishing pad.

Spiral grooved polishing pad for chemical-mechanical planarization of

A method of sputter deposition for improved side wall and bottom coverage of high aspect ratio features on a substrate includes alternatingly exposing the substrate having high aspect ratio features to a collimated sputtered particle flux and a less-collimated sputtered particle flux until a desired deposition thickness is reached. A confining magnetic field may be used to reduce electron losses at process chamber walls, allowing for improved collimation of the collimated flux. The substrate may also be heated or biased during exposure to the less-collimated flux to increase the good side wall and step coverage of the less-collimated flux, and cooled or reverse-biased during exposure to the collimated flux to increase the good bottom coverage of the collimated flux. Alternatively, the substrate may be exposed to only a collimated flux, but good sidewall coverage by be achieved by alternating the temperature and/or bias of the substrate to provide the desired side wall and step coverage.

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Meridian, ID, United States of America

Richard L Elliott