National Semiconductor Corporation

Via Technologies, Inc.

Texas Instruments Corporation

Richard L Duncan

Joseph Douglas Wert

Michael John Shay

William V Miller

Timothy Don Davis

Chuan Ni

Degang Xia

Gordon Force

Thomas M Norcross

Timothy A Short

Steven Chacko

Dan E Daugherty

Daniel Davis

A circuit to protect data on an FRAM during a read operation includes an FRAM voltage regulator having an output to supply an FRAM operating voltage to the FRAM. A voltage monitor monitors a supply voltage for the FRAM to generate a voltage fault signal if the supply voltage falls below a predetermined value. And a circuit responsive to the voltage fault signal maintains the FRAM operating voltage above a voltage required to assure data integrity of the FRAM for a sufficient time required to perform an FRAM read operation.

Fast response circuits and methods for FRAM power loss protection

Systems and methods are disclosed herein for retrieving data from memory in a computer system. In one example, a memory controller is coupled to a system bus in a computer system that includes bus masters similarly coupled to the system bus. The memory controller is configured to receive requests to read or write data from memory from bus masters of the computer system. If the memory controller receives an initial request from certain bus masters, the memory controller is further configured to anticipate a future request from certain bus masters and prefetch data on behalf of certain bus masters for rapid delivery following a subsequent request to read data from memory submitted by the certain bus masters.

Systems and method for improved data retrieval from memory on behalf of bus masters

Included in this disclosure is a circuit for reducing power consumption in a microprocessor. The circuit comprises a microprocessor, at least one full instruction decoder configured to decode a present instruction, and at least one subset instruction decoder configured to determine whether the present instruction potentially needs a register. A memory element is also included and is configured to hold data from a previous instruction. A selector is included and configured to output either the previous instruction or the decoded present instruction, based on the subset instruction decoder.

System, method, and apparatus for reducing power consumption in a microprocessor

The present disclosure illustrates a system for reducing power consumption in a computer processor. Included is a 16-bit instruction decoder for decoding instructions with 16-bit words, a 32-bit instruction decoder for decoding instructions with 32-bit words, a word length select for indicating a present instruction's word length, and a first selector for routing the instruction into the 16-bit decoder when the present instruction is 16-bits long. The first selector is also configured to route a previous instruction into the 16-bit decoder, maintaining the 16-bit decoder's present state. A second selector is configured to route the instruction into the 32-bit decoder when the present instruction is 32-bits long. The second selector is also configured to route a past instruction into the 32-bit decoder to maintain the 32-bit decoder's present state.

System for reducing power consumption in a microprocessor having multiple instruction decoders that are coupled to selectors receiving their own output as feedback

The present invention is generally directed to an apparatus and method for reducing excess power consumption of a bus master circuit component for use in a multi-bus master system. In one embodiment, the bus master is provided in the form of an integrated circuit comprising clock control logic that is configured to disable a clock signal that is otherwise delivered to functional circuitry contained within the integrated circuit during a period of time between the request for mastership of a bus and the grant of that request.

Apparatus and method for assuming mastership of a bus

An improved signal synchronizing circuit for prohibiting signals traveling from a first clock domain operating with a first clock to a second clock domain operating with a second clock when the first clock is not active. The synchronizing circuit comprising at least one signal receiving module for receiving at least one selected signal in the first clock domain, a detection circuit producing a detection signal indicating that the first clock is active, and at least one output selection module for passing the selected signal from the first clock domain to the second clock domain when the first clock is active.

Synchronizer apparatus for synchronizing data from one clock domain to another clock domain

An output driver prevents gate oxide breakdown and reverse charge leakage from a bus to the internal power supply. When the voltage on the bus exceeds the internal supply voltage or when the driver is powered down, a reference voltage generator provides intermediate voltages to prevent the development of excessive gate-source, gate-drain, and gate-backgate voltages in the driver. An upper protection circuit and a lower protection circuit multiplex the intermediate voltages to ensure driver protection and proper operation. A buffering circuit turns off a buffering transistor to block charge leakage to the internal power supply when the bus voltage is greater than the internal power supply voltage. A logic protection circuit prevents the bus voltage from appearing at the control terminal of the driver.

Gate oxide protection method

An output buffer circuit includes multiple programmable boost drive stages which allow selection of one of several drive strengths to accommodate a range of output load conditions, thereby achieving low noise and low power dissipation. In one embodiment, one or more of the boost circuits turn on after the primary driver circuit is turned on, and turn off before the primary circuit is turned off, thereby achieving soft turn-on and turn-off.

Programmable high speed quiet I/O cell

A circuit for voltage translation includes protection against gate oxide breakdown when translating a lower voltage signal into a higher voltage signal. An input signal inverter circuit inverts the lower voltage signal into an intermediate signal having an increased minimum value. By raising the maximum value of the intermediate signal to the voltage level of the higher voltage signal, an output signal inverter circuit produces a driving signal to drive an output stage. However, because the increased minimum value of the signal is maintained, the gate oxide breakdown voltage is not exceeded in the circuit. The circuit also includes a blocking transistor between the input signal inverter and the output signal inverter to prevent the larger driving signal from overloading the input inverter circuit.

Voltage translator with gate oxide breakdown protection

Gate oxide breakdown protection circuit for deep submicron processes

A clock system includes internal monitor circuitry such that the clock system is testable in a secure environment. In particular, the clock system includes a plurality of separately enableable clock generator circuit modules. Each of the clock generator circuit modules generates a separate clock signal when enabled. Combining circuitry receives the separate clock signals from those clock generator circuit modules which are enabled and derives a derived clock signal therefrom. Monitor circuitry receives the derived clock signal, detects whether there are transitions in the derived clock signal, and provides a monitor indication of a result of the detection. Thus, the clock system can be tested without providing the separate clock signals outside the clock system. Preferably, the clock system also includes a programmable clock control register that holds clock control data, the clock control data determining which of the clock generator circuit modules are enabled. A processor is connected to program the clock control data in the clock control register circuitry. The processor executes a program that programs the clock control data to enable and then disable each of the clock generator circuit modules one at a time and to query the monitor indication while each of the clock generator circuit modules is enabled.

Clock system with internal monitor circuitry for secure testing

A circuit connects a circuit node to a voltage source selected between two alternative power supply voltage sources. The circuit includes two transistors, specifically a first transistor selectively connecting the circuit node to a first power supply voltage source of the two alternative power supply voltage sources and a second transistor selectively connecting the circuit node to the second power supply voltage source. The first transistor has a gate connected to the second power supply voltage source. The second transistor has a gate connected to the first power supply voltage source. The circuit passes the lowest voltage supplied by the two alternative voltage sources to the circuit node. The circuit is useful, for example, in a voltage translation and overvoltage protection circuit.

Circuit for connecting a node to a voltage source selected from

The present invention provides input and output buffers which block the charge leakage from the bus to the internal power supply when the bus voltage exceeds the internal power supply voltage or when the buffer is powered down. An isolation transistor is connected in series with a pull-up transistor between the internal power supply and the output terminal which is connected to the bus. A circuit that controls the pull-up transistor in response to an enable signal and a data input signal, controls also the isolation transistor so that when the driver is enabled and the pull-up transistor is on, the isolation transistor is also on allowing the pull-up transistor to drive the output terminal. A transistor between the circuit and the isolation transistor gate isolates the gate from the circuit when the driver is disabled. Thus, when the driver is disabled, the circuit does not control the isolation transistor. Instead, the isolation transistor is controlled by a pass-through transistor connected between the gate of the isolation transistor and the output terminal. When the driver is enabled, the pass-through transistor is off. When the driver is disabled and the output terminal voltage exceeds the predetermined value, the pass-through transistor turns on to turn off the isolation transistor. The isolation transistor is a PMOS transistor in some embodiments. The isolation transistor drain and backgate are connected to turn off the drain/backgate diode.

Overvoltage protection

A voltage translator is provided that translates a lower voltage to a higher voltage, for example, a 3.3 V voltage to a 5.0 V voltage. The 3.3 V voltage is received on source/drain terminal N1 of an NMOS transistor. The transistor gate is at 3.3 V. The other source/drain terminal N2 of the transistor is connected to an input of a CMOS inverter powered by 5.0 V. The inverter output is connected to the gate of a PMOS transistor connected between 5.0 V and terminal N2. The PMOS transistor pulls terminal N2 to 5.0 V when terminal N1 is at 3.3 V. The same translator is suitable for translating a 5.0 V voltage on terminal N1 to 3.3 V on terminal N2 if the inverter is powered by 3.3 V and the PMOS transistor is connected between 3.3 V and terminal N2. Also, an output driver is provided in which a voltage protection circuitry prevents charge leakage from the driver output terminal to the driver's power supply when the voltage on the bus connected to the output terminal exceeds the power supply voltage.

Voltage translation and overvoltage protection

The present invention is embodied in a Secured Processing Unit (SPU) chip, a microprocessor designed especially for secure data processing. By integrating keys, encryption/decryption engines and algorithms in the SPU, the entire security process is rendered portable and easily distributed across physical boundaries. The invention is based on the orchestration of three interrelated systems: (i) detectors, which alert the SPU to the existence, and help characterize the nature, of a security attack; (ii) filters, which correlate the data from the various detectors, weighing the severity of the attack against the risk to the SPU's integrity, both to its secret data and to the design itself; and (iii) responses, which are countermeasures, calculated by the filters to be most appropriate under the circumstances, to deal with the attack or attacks present. The present invention, with wide capability in all three of the detectors, filters and responses, allows a great degree of flexibility for programming an appropriate level of security/policy into an SPU-based application.

Growing community of inventors

Bedford, TX, United States of America

Richard L Duncan