Bull Hn Information Systems, Inc.

Richard L Demers

Ronald E Lange

Wilbur L Stewart

Russell Wayne Guenthner

William A Shelly

Ronald W Yoder

Lowell D McCulley

Jeffrey D Weintraub

In order to reduce the size of the memory employed to store firmware, the firmware is written in virtual control words which are then reduced by allotting them to a primary control word memory and at least one secondary control word memory which is addressed by a field in the primary control word memory. A virtual set of secondary control words are each divided into a plurality of fields, and each field of each secondary virtual control word is marked as guarded or 'don't care'. If a field is marked as 'don't care', the function represented by the virtual control word will perform properly no matter what the content of that field. Virtual control word pairs are then examined to ascertain if they can be combined into a single control word. If the guarded fields in the first virtual control word align with the 'don't care' fields in the second virtual control word and vice versa, the two virtual control words can be combined into a single control word containing the contents of the guarded fields from both virtual control words, the remaining fields, if any, remaining 'don't care'. This process may be reiterated to determine if the combined control word can be further combined with another virtual control word. In operation, all the functions represented by a combined control word are executed by calling for that single control word stored in the secondary control word memory.

Method for reducing control store space in a VLSI central processor

In order to efficiently undertake the micro-steps required to execute an extended instruction in a central processing unit, a main sequence controller and a separate basic operations controller having its own sequencer and the ability to run semi-autonomously are provided. Normally, the main sequence controller determines the operation of the basic operations controller, but, in the case of execution of, for example, a multi-word instruction requiring extended basic operations, the basic operations controller temporarily takes control over the main controller until the extended basic operations have been completed. The result is a relatively simple sequencer that supports tight micro-coded functions where many of the sequence decisions can be predetermined.

Basic operations synchronization and local mode controller in a VLSI

Method and apparatus to reduce the number of control words stored in a read only control store of a microprogrammed unit of the CPU of a large scale computer. A set of control fields are required to control the active elements of the unit to cause the unit to execute a large number of different basic operations. Typically the required set of control fields are included in control words stored in a control store controlling the unit during the execution of a basic operation. Obtaining some of the set of required control fields from other sources available within the unit results in a significant reduction in the number of control words stored in the control store without reducing the functionality of the unit.

Method and apparatus for minimizing the number of control words in a

In a central processor incorporating at least one co-processor, such as a floating point arithmetic co-processor, in addition to a basic arithmetic logic unit, the problem of rationalizing the contents of the accumulator and supplementary accumulator registers without the burden of speed penalties is addressed and solved. This is achieved by providing input/output access to a common register file and by switching control of the register file to the proper processing unit appropriately. A single, shared accumulator register and a single, shared supplementary accumulator register are included in the stack along with other sharable registers such as address modification registers. Thus, the contents of the accumulator register and the supplementary accumulator register are always up-to-date and available to all processing units in the central processor without the need for first carrying out rationalization steps.

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Peoria, AZ, United States of America

Richard L Demers