Tactical Fabs, Inc.

Quicklogic Corporation

Fujitsu Corporation

Richard L Bechtel

Mammen Thomas

James W Hively

Andrew K Chan

Ralph G Whitten

John M Birkner

Hua-Thye Chua

Hassan O Ali

Wen C Ko

Douglas L Peltzer

William T Liggett

A clamping system decouples the clamping forces in an electrical circuit assembly coupled to a heatsink. A heatsink clamping assembly applies controllable and predictable force on the electrical circuit assembly including an integrated circuit device (&ldquo;chip&rdquo;). The applied force is controlled to effectively ensure intimate contact between the chip and the heatsink to facilitate efficient chip cooling. The force applied to the chip is decoupled from the much higher force required to clamp the electrical interposer interconnect structure between the electrical circuit assembly and the printed circuit board.

Heatsink apparatus for de-coupling clamping forces on an integrated circuit package

In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Method for fabrication of programmable interconnect structure

In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for forming a field programmable gate array with antifuses.

Electrically programmable interconnect structure having a PECVD

A field programmable gate array has a programmable interconnect structure comprising metal signal conductors and metal-to-metal PECVD amorphous silicon antifuses. The metal-to-metal PECVD amorphous silicon antifuses have an unprogrammed resistance of at least 550 megaohms and a programmed resistance of under 200 ohms.

Field programmable gate array having reproducible metal-to-metal

This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned to accomplish multiple purposes. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure (for a memory wafer the word length, number of banks of words, and number of words per bank). The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing (testing uses conventional techniques) for good and bad elements. As another novel feature, the structure may include two or more address ports, which may simultaneously address different banks of the repeating elements. The plural address port feature is particularly useful for automatic refreshing of dynamic random access memories (DRAMs) and/or for plural addressing with other memory types. The architecture provides for flexibility in the final functional organization of wafer scale devices, which is determined at the time the via level is customized. An overall reduction of overhead control circuitry and the reduced size of the repeated block provides for higher total density per wafer than is achievable with conventional single chip integrated circuits using the same level of manufacturing technology. More than one discretionary via layer and more than one bus layer may be provided.

Very high density wafer scale device architecture

This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure. The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing for good and bad elements. The structure may include two or more address ports, which may simultaneously address different banks of the repeating elements, which feature is particularly useful for automatic refreshing of dynamic random access memories (DRAMs) and/or for plural addressing with other memory types. The architecture provides for flexibility in the final functional organization of wafer scale devices, which is determined at the time the via level is customized. An overall reduction of overhead control circuitry and the reduced size of the repeated block provides for higher total density per wafer than is achievable with conventional single chip integrated circuits using the same level of manufacturing technology.

This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned to accomplish multiple purposes. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure (for a memory wafer the word length, number of banks of words, and number of words per bank). The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing (testing uses conventional techniques) for good and bad elements.

A package for housing a large scale semiconductor integrated circuit structure, such as a wafer or an assemblage of chips in a hybrid configuration, comprises a heat spreading and dissipating base plate to which the wafer or hybrid circuit is directly bonded. Electrical connections from the periphery of the package interior to the wafer are preferably made with equal length TAB (Tape Automated Bonding) strips connected to electrically conductive pads located along a diameter of the wafer or the centerline of the hybrid circuit. If hermeticity is desired, the integrated circuit structure is encircled by a boundary strip of sandwich construction through which signals are routed, and to which a lid is attached. For hermeticity, the integrated circuit structure is surrounded on all sides with a barrier combining metal and ceramic; the remainder of the package may be constructed from conventional printed circuit board materials. The package can be made arbitrarily large without encountering the problems typically associated with hermetic structures which utilize large areas of ceramic materials.

Package for an integrated circuit structure

A package for multiple semiconductor integrated circuit chips uses an interconnect structure manufactured by semiconductor processing techniques to provide dense interconnections between chips and to input/output terminals. Chips are thermally connected to a Kovar or molybdenum heatsink. The interconnect structure is constructed by fabricating multiple layers of interconnect metallization on an optically flat glass (or other dielectric) surface patterned into lines and separated by smoothed glass dielectric. The metallization lines are interconnected by vias and lead to pads which are connected to chip pads and to exterior pins or wiring. An interconnect frame allows access to the chips and the interconnect structure to effect wire bonding of the chips to the metallization and provide sealable cavities for the chips. Elastomeric connectors extend through and are aligned by the frame to connect pads on the interconnect structure top to traces on a mother board to which the package is mounted. Chip bonding plates allow chips to be removed from the package and replaced when found defective.

High density multichip package with interconnect structure and heatsink

A point contact solar cell structure and method of manufacturing which provides metal contact from positive and negative bus bars to alternating n-wells and p-wells in a solar cell crystal. The solar cell spans two side-by-side metal bus bars. On the bottom surface of the cell crystal two side-by-side perforated metal layers contact wells of only one conductivity type. Holes in the perforated metal layers are located beneath wells of the opposite conductivity type. An insulated junction between the two perforated metal layers is located directly above the junction between the two side-by-side metal bus bars. Fingers from the perforated metal layer above one bus bar reach across and down to contact the opposite bus bar. Metal lines also reach from the bus bars up through the holes in the perforated contact layers and contact wells within the crystal. This way, all n-wells and p-wells have electrical contact to their respective bus bars. A preferred embodiment includes a passivation layer applied to top and sides of the solar cell after dicing thus providing an anti-reflection coating on the top surface and means for reducing recombination of electrons and holes at edges of the solar crystal back to the interior of the crystal for capture by a p-well or n-well. Benefits include increased cell efficiency, reduced number of masking steps in the manufacturing process as compared to other point contact structures, and improved thermal conductivity through the cell, resulting in lower manufacturing cost and longer cell life.

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Sunnyvale, CA, United States of America

Richard L Bechtel