Ncr Corporation

Richard Kruithof

Hans Van Driest

Hendrik Van Bokhorst

In a delay measuring circuit (10), an input clock signal (13) is applied to a multitapped delay line (14), the output taps of which are connected to a switch (26) which selects one of the switch inputs for connection to a phase comparator (34) which compares the input clock signal (13), delayed in a delay device (38) to compensate for the delay inherent in the switch (26), with the output of the switch (26). The input clock signal is also applied to a counter (22), and when the phase comparator (34) detects a phase match, the counter value is stored in a latch (32), the counter (22) is reset to a predetermined value, and the counting procedure resumed. The latch (32) thus always stores a value dependent on the delay of an individual delay cell (16-l to 16-N). This stored value can be applied to various uses, such as in a timing watchdog circuit or for generating accurate delays.

Delay measuring circuit

A digital phase lock loop decoder for use in decoding Manchester encoded data operates at an internal clock speed having a speed equal to the data rate of the encoded data. The decoder includes a first sampling circuit for providing signals based on the clock speed of the encoded data, a delay circuit for generating delayed clock signals relative to the clock speed of the encoded data, a second sampling circuit for sampling the encoded data based on the delayed clock signals, a feedback circuit for generating clock signals whose phase corresponds with the phase of the delayed clock signals and a storage for outputting decoded data signals corresponding to the encoded data utilizing the delayed clock signals.

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Voorschoten, Netherlands

Richard Kruithof