Agilent Technologies, Inc.

Hewlett-packard Company

Avago Technologies General IP (singapore) Pte. Ltd.

Richard Keith Karlquist

John Dwight Larson, Iii

Herbert L Ko

Kent W Carey

Mark A Hueschen

Leonard S Cutler

Robin P Giffard

James L Johnson

Theodore Parisek

James R Collin

A downconverter mixes a first comb spectrum with a local oscillator signal to generate a second comb spectrum in a lower frequency range. The first comb spectrum comprises frequency components separated from each other according to a frequency spacing interval, and the LO signal has a frequency offset relative to the first comb spectrum, where the frequency offset is a rational fraction of the frequency spacing interval. The second comb spectrum comprises lower and upper sideband responses corresponding to respective lower and upper sideband signals of the first comb spectrum. The lower and upper sideband responses in the second comb spectrum can be distinguished from each other based on the frequency offset.

Downconversion of comb spectrum

A split-band system for processing a broadband input signal is disclosed. A signal divider divides the input signal into at least a higher frequency band and a lower frequency band. The lower frequency band is processed in a lower frequency circuit path. The higher frequency band is processed in a higher frequency circuit path. The higher frequency circuit path has a group delay equal to the lower frequency circuit path. A signal combiner combines the processed lower frequency band and the processed higher frequency band into an output signal.

Split band signal processing

A substantially passive implementation of a clock recovery circuit may be employed to reduce or eliminate the amount of jitter added to the recovered clock by the recovery circuitry. NRZ data may be received in differential form (i.e., a separate NRZ signal and an inverted NRZ signal are received). The inverted NRZ data may be delayed by one-half of a unit interval with respect to the NRZ data by a delay element. The NRZ data and the delayed NRZ data may be combined by a broadband combiner (e.g., a resistive adder). The combined signal may be split into two signals. The two split signals may be rectified by suitable components. One of the limited split signals may be subtracted from the other limited split signal to generate an output signal. The generated output signal then possesses a spectral component at a clock frequency of the NRZ data.

System and methods of recovering a clock from NRZ data

An electro-optic delay line frequency discriminator has an optical signal source providing first and second optical signals that are directed along first and second paths, respectively. In the first path, the first optical signal is converted to a first corresponding optical signal that corresponds to an electrical input signal, and the first corresponding optical signal is then delayed. In the second path, the second optical signal is delayed, and the delayed second optical signal is then converted to a second corresponding optical signal that corresponds to the electrical input signal. The first and second corresponding optical signals are converted to first and second corresponding electrical signals, respectively; and a detector, responsive to the first and second corresponding electrical signals, provides an electrical output signal from the discriminator. Optical source relative intensity noise (RIN) is canceled out and does not degrade the signal-to-noise ratio of the discriminator output.

Electro-optic delay line frequency discriminator

In one embodiment, the present invention is directed to a system for processing a data stream. The system comprises: a voltage controlled oscillator (VCO) that generates a VCO signal in response to a tuning signal; a phase detector that generates an error signal that is indicative of a phase difference between a data signal and the VCO signal; a first filter that filters a reference signal that is indicative of an occurrence of a data transition; a second filter that filters the error signal, wherein the first filter and second filter are low-pass filters that possess a bandwidth that approximately equals one half of the reciprocal of: a unit interval multiplied by a maximum run length; and a divider circuit that divides the filtered error signal by the filtered reference signal.

Systems and methods for correcting gain error due to transition density variation in clock recovery systems

A method and apparatus for synchronizing multiple-stage multiplexers are disclosed. According to exemplary embodiments of the present invention, multiplexer circuits in the multiple-stage multiplexer are synchronized based upon a frequency response of the output of the multiplexer. The power level of the output of the multiple-stage multiplexer is measured at a frequency corresponding to the input data rate of the multiple-stage multiplexer, during the time a test pattern is sent through the multiple-stage multiplexer. In an exemplary embodiment of the invention, the multiple-stage multiplexer is placed in substantially random states until the measured power level reaches the predetermined.

Method and apparatus for synchronizing a multiple-stage multiplexer

A frequency translating device (FTD) includes at least one mixer diode connected to down-convert a radio frequency (RF) to an intermediate frequency (IF) and to up-convert an IF to an RF and a source of direct current (DC) bias that is connected to the mixer diode. The source of DC bias provides DC bias to the mixer diode that moves the voltage applied to the mixer diode closer to the threshold voltage of the mixer diode. The mixer diode is turned on in response to the DC bias and a local oscillator (LO) drive. Because DC bias is applied to the mixer diode, the peak to peak voltage range of the LO drive can be reduced, thereby reducing the voltage-dependent capacitance of the mixer diode, causing the FTD to exhibit improved reciprocity. The FTD can be used in a three-pair measurement system to determine the conversion response of another FTD.

Frequency translating devices and frequency translating measurement systems with DC bias added to a mixer diode

A frequency multiplexer is disclosed. The frequency multiplexer comprises a lumped element transmission line comprising a plurality of inductances and capacitances, and a band pass filter coupled to a node of the lumped element transmission line, where the band pass filter includes a branch port that is coupled to the lumped element transmission line at a pass band of the band pass filter, and where the band pass filter exhibits a capacitive impedance in a stop band of the band pass filter. The band pass filter may comprise a series resonant circuit and a parallel resonant circuit, where the parallel resonant circuit is parallel resonant at nominally the same frequency at which the series resonant circuit is series resonant. An additional series resonant circuit may be coupled to the lumped element transmission line, where, at a resonant frequency of the additional series resonant circuit, the additional series resonant circuit is located at an electrical length of 90 degrees away from the series resonant circuit and the parallel resonant circuit on the lumped element transmission line, where the additional series resonant circuit exhibits a capacitive impedance at off-resonant frequencies.

Lumped element transmission line frequency multiplexer

A frequency translating device (FTD) includes at least one light-activated resistor (LAR) connected to down-convert a radio frequency (RF) to an intermediate frequency (IF) and to up-convert an IF to an RF and a source of modulated light that is optically connected to the LAR. The source of modulated light is modulated in response to a local oscillator (LO) and the LAR is activated in response to the modulated light. Modulated light can be generated from a light source and an LO by, for example, directly modulating the light source, modulating a transmission switch that blocks the transmission of light to the LAR, or modulating a light path switch. The LAR-based FTD can be used as a reciprocal FTD to characterize another FTD in a three-pair measurement system. An FTD may include more than one LAR to form, for example, single-balanced and double-balanced LAR-based FTDs.

Frequency translating devices and frequency translating measurement systems that utilize light-activated resistors

Tracking error in phase locked loop (PLL) devices is addressed utilizing feed-forward phase modulation. Specifically, the phase difference of the reference signal and said oscillator signal of a PLL may be determined utilizing a phase detector. The output of the phase detector may be provided to a loop filter to provide feedback to the VCO of the PLL. Additionally, the filtered phase difference may be provided to a suitably calibrated phase modulator to add an amount of phase modulation to the oscillator signal that is approximately equal and opposite to said phase difference to generate a corrected phase output signal.

Systems and methods for correcting phase locked loop tracking error using feed-forward phase modulation

A circuit and method are disclosed for adjusting the clock skew in a synchronous system. The circuit and method include initially applying an offset voltage to a data input of a device in the system. Next, the clock skew between a device and a data source providing data thereto is adjusted to approximately 180 degrees, by selecting the clock skew resulting in an approximately maximum DC offset appearing at the output of the device. Thereafter, the clock skew is shifted from approximately 180 degrees to the desired clock skew amount.

Circuit and method for adjusting the clock skew in a communications system

A modulation domain divider is disclosed that causes the divider output to be attenuated when the divisor input falls below the divisor threshold. Attenuation is accomplished by implementing the divider in the modulation domain and substituting an unmodulated signal for the normal modulated signal when the divisor is below the threshold value.

System and method for divisor threshold control in a modulation domain divider

In embodiment, the present invention is directed to a PLL phase demodulator that utilizes feed-forward error correction. The feed-forward error correction may occur by calibrating an equalizer to possess transfer function that emulates the modulation response curve of the VCO of the PLL phase demodulator. In operation, the equalizer may receive the filtered and integrated version of the error signal produced by the phase detector of the PLL. The equalizer filters the received signal according to the calibrated transfer function. The output of the equalized is provided to a adder to combine the equalized signal with the error signal produced by the phase detector. A similar arrangement including a suitably calibrated equalizer may be utilized to address phase tracking error in a PLL frequency demodulator.

Phase locked loop demodulator and demodulation method using feed-forward tracking error compensation

A computation circuit operates in the modulation domain to generate a signal having phase modulation proportional to the ratio of the dividend (numerator) signal to the divisor (denominator) signal. The phase modulated signal may be demodulated by a phase demodulator to produce a baseband quotient signal. The divisor signal maintains inverse proportional control of the modulation gain of the modulator by varying the carrier injection level, resulting in higher bandwidth and accuracy, and lower drift and offset compared to traditional analog computation techniques. The circuit may contain all linear components, even though the division function is a non-linear function. The circuit and method operate when the input signals are analog or both are in the modulation domain.

System and method for designing and using analog circuits operating in the modulation domain

Phase detector constructed from a plurality of multi-input gates which combine combinations of unretimed input data with retimed data and with clock signals to achieve output pulses proportional to the phase difference between the unretimed data and the clock. In the embodiment the phase detector comprises an input for receiving data signals; an input for receiving clock signals; an output for providing phase control signals; data retiming circuitry for accepting unretimed data signals from said data input and for providing even and odd retimed signals therefrom; a plurality of multi-input gates having inputs connected to different combinations of said unretimed data signals, said retimed data signals, and said clock signals, such that no said gate can be active in two consecutive UIs, when a UI is defined as the length of time allocated to a single bit; and a combiner for mixing the outputs of at least two of said gates.

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Cupertino, CA, United States of America

Richard Keith Karlquist