Advanced Micro Devices Corporation

Richard K Klein

Raymond T Lee

Craig S Sander

Stephen C Horne

Christopher A Spence

John Christian Holst

Asim A Selcuk

Nicholas John Kepler

Steven C Avanzino

Robin W Cheung

Ming-Ren Lin

Subhash Gupta

Scott D Luning

Darrell M Erb

Mario M Pelella

Bryan M Tracy

Pankaj Dixit

Tat C Choi

Mohammad Farnaam

Jack Sliwa

William George En

Srinath Krishnan

Dong-Hyuk Ju

Amy C Tu

James D Werking

Siu Lun Lee

A method is provided for fabricating a silicon on insulator (SOI) device that includes a silicon substrate, a buried insulator layer overlying the silicon substrate, and a monocrystalline silicon layer overlying the buried insulator layer. The method comprises the steps of forming an MOS capacitor coupled between a first voltage bus and a second voltage bus. The MOS capacitor has a gate electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the gate electrode material forming a second plate of the MOS capacitor. The first voltage bus is coupled to the first plate of the capacitor and the second voltage bus is coupled to the second plate of the capacitor. The method further includes forming an electrical discharge path coupling the second plate of the MOS capacitor to the silicon substrate.

Method for fabricating an SOI device

A method and apparatus for reducing the number of stages for measuring first and second switching speeds for PD/SOI transistors uses an inverter circuit which includes: a p-channel body-tied transistor; an n-channel body-tied transistor, coupled at their drains and gates; and a first and a second group of components tied to the bodies of the transistors. The first group restores body potentials for the transistors if the inverter circuit belongs to an even numbered stage of a ring oscillator. The second group provides body potentials for the transistors if the inverter circuit belongs to an odd numbered stage. After each transition of a waveform, the body potentials for the PD/SOI transistors are restored to the original potentials as stored in the capacitors. In this manner, a much smaller ring oscillator with fewer number of stages may be used to accurately measure the first and second switching speeds.

Emulation of long delay chain by ring oscillator with floating body-tied body devices

A multiple independent bit Flash memory cell has a gate that includes a first oxide layer, a discontinuous nitride layer on the first oxide layer, a second oxide layer on the discontinuous nitride layer and the first oxide layer, and a polysilicon layer on the second oxide layer. The discontinuous nitride layer has regions residing at different portions of the layer. These portions are separated by the second oxide layer. Thus, with a smaller channel length, charge that otherwise would migrate from one region to the other and/or strongly influence its neighboring it is blocked/impeded by the second oxide layer. In this manner, the potential for charge sharing between the regions is reduced, and a higher density chip multiple independent bit Flash memory cells may be provided.

Discontinuous nitride structure for non-volatile transistors

An integrated test circuit for a silicon on insulator circuit structure is formed on the same wafer as the circuit structure. The wafer includes an input circuit coupled to the silicon on insulator circuit structure which generates a drive signal for operating the silicon on insulator circuit structure and an output circuit which processes a response signal from the circuit structure to generate an output signal representing certain characteristics of the silicon on insulator circuit structure.

Device and method for testing performance of silicon structures

A device structure and a method of forming the structure comprising a resistor in a via opening between adjacent levels of metallization of a conventional field effect transistor (FET) by using amphorous (&agr;) silicon between metal barrier layers, such as titanium tungsten and titanium nitride, at the via opening which is filled with a conductive material, such as tungsten said device structure and method enabling a conventional FET and resistor to only take the space of a conventional FET due to the unique properties of &agr;-silicon.

Method of forming four transistor SRAM cell having a resistor

A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening, and using the sidewalls as a mask to remove, preferably by etching, a portion of the conductive line pattern substantially equal in size to the reduced opening.

Forming minimal size spaces in integrated circuit conductive lines

A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET. A portion of an insulating layer between the source and drain is removed prior to forming the gate. Preferably, an etch stop layer on the semiconductor substrate underlying the insulating layer is used in the method.

Minimizing transistor size in integrated circuits

A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect metallization can be misaligned and the selected gates will be protected by its etch barrier and not be exposed to the opening. Further, local interconnect conductive material can pass over a gate or unrelated resistor without shorting the gate/resistor.

Forming local interconnects in integrated circuits

A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.

Method for self-aligning polysilicon gates with field isolation and the

A device structure and a method of forming the structure comprising a thin film transistor (TFT) in a contact opening of a conventional field effect transistor (FET) by using .alpha.-silicon in the opening and the vertical portion of the .alpha.-silicon functioning as the channel for the TFT and both the FET and TFT sharing a common drain contact.

P-channel thin film transistor having a gate on the drain region of a

A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to selectively ion implant oxygen into the polysilicon and annealing to convert the oxygen implanted polysilicon to silicon oxide. As an alternative method, an opening in an insulating layer overlying the conductive line is first formed by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening and using the sidewalls as a mask to blanket implant oxygen through the reduced opening and into the exposed polysilicon conductive line. After annealing, the implanted polysilicon converted to silicon oxide and removed to form a gap or space in the polysilicon conductive line pattern substantially equal in size to the reduced opening. Instead of blanket implanting with oxygen, thermal oxidation can be used to convert the exposed polysilicon to silicon oxide.

A device structure comprising a resistor in a via opening between adjacent levels of metallization of a conventional field effect transistor (FET) by disposing amorphous (.alpha.) silicon between metal barrier layers, such as titanium tungsten and titanium nitride, at the via opening which is filled with a conductive material, such as tungsten, the device structure enabling a conventional FET and the resistor to only take the space of a conventional FET due to the unique properties of .alpha.-silicon.

Four transistor SRAM cell

A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure. The capacitive structure includes a dielectric material between polysilicon conductive lines and tungsten local interconnects. The polysilicon plates are each connected to drains of lateral transistors associated with the SRAM cell. A dielectric material such as silicon dioxide may be deposited between the local interconnect and polysilicon conductive lines. The capacitor structures are provided between first and second N-channel pull down transistors associated with the SRAM cell.

Memory cell having increased capacitance via a local interconnect to

A memory device uses a reduced word line voltage during READ operations. The memory device includes a memory cell and a pass transistor for accessing the cell. The cell includes a storage node coupled to a pull-down transistor having substantially the same conductivity as the pass transistor. A drive circuit generates a reduced word line voltage to activate the pass transistor during a READ operation. The reduced word line voltage has a magnitude less than the magnitude of the bias voltage used to activate the pull-down transistor.

Memory device using a reduced word line voltage during read operations

A multilayer semiconductor structure includes a conductive via. The conductive via includes a reservoir of metal having a high resistance to electromigration. The reservoir is made from a conformal layer of copper, or gold deposited over the via to form a copper, or gold plug located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the reservoir from diffusing into the insulating layer. The barrier layer and reservoir may be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and reservoir may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

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Mountain View, CA, United States of America

Richard K Klein