Texas Instruments Corporation

Iowa State University Research Foundation Inc

Richard K Hester

Patrick Peter Siniscalchi

Khen-Sang Tan

Timothy Patrick Pauletti

William J Bright

Suheng Chen

Donald Cook Richardson

Michiel De Wit

Amneh Mohammed Akour

Nat Maruthachalam Natarajan

Jayanth Rangaraju

Marco Corsi

Cetin Kaya

John William Fattaruso

Weibiao Zhang

Kenneth George MacLean

Glenn H Westphal

Nagarajan Sridhar

Philip Sean Stetson

Lin Wu

James Donald Quarfoot

Minsheng Wang

Sairaj Vijaykumar Dhople

Nuboru Shiwaku

A controller circuit for a PV sub-module includes a power harvest controller circuit, a voltage limit controller circuit, a power mode control circuit, a multiplexer circuit, and a switching converter circuit. The power harvest controller circuit, including a first PV voltage input, a ceiling reference input, a floor reference input, and a first gate control output. The voltage limit controller circuit, including a first output voltage feedback input, a pulse width reference input, and a second gate control output. The power mode control circuit, including a second output voltage feedback input, a mode reference input, and a mode selection output. The multiplexer circuit, including a first gate control input, a second gate control input, a mode selection input, and a third gate control output. The switching converter circuit, including a second PV voltage input, a third gate control input, and a DC voltage output.

Controller circuit for photovoltaic sub-module

Series strings of photovoltaic (PV) modules with integrated dc-dc microconverters that can function in buck, boost, or an intermediate bridge mode based on the load can harvest more energy than conventional central-inverter architectures, especially when the arrays are partially shaded or when the modules are mismatched. The integrated multi-mode dc-dc converter includes a maximum power point tracking (MPPT) algorithm that can track the true MPP, even when a PV module becomes partially-shaded, without scanning the entire output voltage range. The algorithm compares power levels only at a voltage that occurs when a bypass diode bypasses a portion of an associated PV module, and multiples thereof.

High efficiency wide load range buck/boost/bridge photovoltaic micro-converter

Traditionally, buck-boost switching regulators with bridge topologies have been avoided due to their inability to seamlessly transition between buck mode and boost mode. Here, however, a buck-boost switching regulator with a bridge topology has been provided, which has an improved controller. Namely, a processor (such as a digital signals processor or DSP) provides digital control for the bridge that reduces ripple current or variations in the inductor current by adjusting phase relationships between corresponding buck and boost switches in a bridge or buck-boost mode.

Switching method to reduce ripple current in a switched-mode power converter employing a bridge topology

Traditionally, buck-boost switching regulators with bridge topologies have been avoided due to their inability to seamlessly transition between buck mode and boost mode. Here, however, a buck-boost switching regulator with a bridge topology has been provided, which has an improved controller. Namely, a processor (such as a digital signals processor or DSP) provides digital control for the bridge to enable it so substantially seamlessly transition between buck mode and boost mode.

Switching method to improve the efficiency of switched-mode power converters employing a bridge topology

A class DH amplifier is provided. The amplifier is generally comprised of a tracking power supply, a class D amplifier section, and a carrier generator. The tracking power supply receives a supply voltage and an analog input signal, and the tracking power supply provides an input for the carrier generator. Based on its input from the tracking power supply, the carrier generator can output a positive ramp signal and a negative ramp signal to the class D amplifier section. The class D amplifier section can generate an output signal base on the analog input signal and the ramp signals from the carrier generator.

Class DH amplifier

A low-EMI switched circuit comprises two or more switches, wherein impedance transitions of the switches are overlapped and the overlap is varied using variable switch timing based on an output power level of the switched circuit. The variable timing results in a variable impedance overlap between the switches. In one example, when one switch turns off (begins a low to high impedance transition) and a second switch turns on (begins a high to low impedance transition), a greater timing delay in beginning the second switch's transition results in a higher switch impedance overlap than a shorter delay does. If the variable timing is based on output power of the switched circuit, the variable delay can operate to reduce fly-back voltages at high power output levels and reduce shoot-through current at lower power levels, reducing EMI and quiescent current of the switched circuit.

Variable timing switching system and method

One-sided pulse width modulated (PWM) amplifiers are disclosed. An example amplifier includes an integrator to receive first and second analog signals, and to output a first amplified signal and a second amplified signal based on the first and second analog signals, a reference changer coupled to the integrator to determine whether a first amplitude is higher than a second amplitude based on the first and second analog signals, to selectively cause the integrator to apply a first resistance between a reference node and the first amplified signal and apply a second resistance between the reference node and the second amplified signal when the first amplitude is higher than the second amplitude, and to selectively cause the integrator to apply the second resistance between the reference node and the first amplified signal and apply the first resistance between the reference node and the second amplified signal when the second amplitude is higher than the first amplitude, and first and second comparators coupled to the integrator to receive the first and second amplified signals, to compare the first and second amplified signals to a reference signal, and to output first and second pulse width modulated signals having respective first and second pulse widths based on the comparisons between the first and second amplified signals and the reference signal.

One-sided switching pulse width modulation amplifiers

Systems and methods for reduced distortion in a class D amplifier are provided. An 'ideal' digital output signal is produced. The 'ideal' digital output signal is then compared to the actual output signal in an error amplifier. The integrator input is the difference between the output stage waveform and the ideal output stage waveform. The net input to the integrator now comprises the imperfections of the power stage, and the feedback loop drives their average to zero. This error is then amplified and integrated. The integrated signal is than applied to a summer where it is added to the analog input. Then as in the typical Class D amplifier, the integrated signal is compared in an error amplifier to a ramp signal generated from the ramp generator.

Systems and methods of reduced distortion in a class D amplifier

Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the present invention provide apparatuses including a power supply, an output, and a composite switch connected between the power supply and the output. The composite switch includes a plurality of transistors connected in parallel, a switch closing delay line having a plurality of switch closing outputs each connected to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each connected to one of the plurality of switch closing outputs. The switch closing delay line and switch opening delay line are connected in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time.

Switching system with reduced EMI

Systems and methods are described herein for changing the frequency response of a filter, such as a hybrid circuit. One or more tunable components are adjustable to provide the hybrid circuit with a frequency response corresponding to the characteristics of an associated communications network, such as a digital subscriber link.

Tunable filter to facilitate communications

A codifier/decodifier (CODEC) filter circuit () connected in a subscriber line interface circuit () includes a transmit section () for converting differential voltage audio transmit signals representing voice transmissions from the subscriber instrument () into encoded digital data for transmission to the digital switching network. A receive section () coupled between the digital switching network and subscriber instrument () within CODEC () for converting encoded digital data representing voice signals switched through the digital switching network to differential voltage audio receive signals for transmission to the subscriber instrument (). The subscriber loop and subscriber instrument () reflect the digital voltage audio signals to the transmit section (). An impedance section () within CODEC () connects between the transmit section () and the receive section () and is disposed to provide an audio band feedback signal between the transmit section () and the receive section () for synthesizing a source impedance for the subscriber line that matches the subscriber loop impedance. Impedance section () includes an analog impedance scaling network () coupled between the transmit section () and receive section (). The impedance section () also includes a programmable digital filter () coupled to the transmit section () having a transfer function equal to:()(1)/((2)(1+(&#x2212;2)/(2))where Ris the second subscriber loop impedance, Cis the subscriber loop capacitance, Ris the first subscriber loop impedance, T is the sampling rate of the analog-to-digital converter and z is the frequency of the signal. Furthermore, a summer circuit () provides feedback between the programmable digital filter () and the receive section () by summing the single-ended audio receive signals from the digital switching network with the audio band feedback signal output by the programmable digital filter ().

Universal impedance matching network for the subscriber line integrated circuits

The asymmetric digital subscriber line receive channel includes: first and second external resistorsandcoupled to a telephone lineand; a coarse programmable gain amplifier CPGA formed in a low voltage process having inputs coupled to the first and second external resistorsand; and a fine programmable gain amplifier PGAcoupled to an output of the coarse programmable gain amplifier CPGA, and having a very fine gain trim adjustment to compensate for a mismatch between the external resistorsandand the coarse programmable gain amplifier CPGA.

ADSL front-end in a low voltage process that accommodates large line voltages

A hybrid circuit has a transfer function having three zeros and four poles that are realized using only two fully-differential amplifiers in combination with a small plurality of resistors and capacitors, making the hybrid suitable for use with a communication medium comprising capacitively coupled non-ideal transformers and transmission lines while providing remarkably good hybrid rejection without the use of inductors.

Active hybrid circuit

The present invention provides an apparatus and method for operating driver amplifier ( ) of a line driver circuit ( ) from a lower set of power supply voltages, and from a higher set of voltages only when the amplitude of the signal ( ) being transmitted by the line driver ( ) requires it as determined by a comparator ( ). Advantageously, this reduces the power dissipation in the line driver ( ) by operating the line amplifier ( ) the majority of the time from the lower supply voltage. A delay circuit ( ) delays the signal to be amplified sufficient to allow the transitioning of the power supply voltages provided to the amplifier hysteresis of this power supply voltage switching may also be used to further reduce power dissipation.

Growing community of inventors

Whitewright, TX, United States of America

Richard K Hester