Cypress Semiconductor Corporation

Suvolta, Inc.

Netlogic Microsystems, Inc

Dsm Solutions, Inc.

Richard K Chou

Damodar Reddy Thummalapally

Andrew L Hawkins

Stefan P Sywyk

Paul H Scott

Pidugu L Narayana

Sanjay M Wanzakhade

A memory cell includes a first access transistor, first and second pull-up transistors, a depletion transistor, and first and second pull-down transistors. The first access transistor is connected to a word line and connected between a first bit line and a first data node. The first pull-up transistor is connected to a first power supply point and the second pull-up transistor is connected to the first power supply point and the second data node. The first pull-down transistor is connected to a second power supply point and to the first data node and the second pull-down transistor is connected to the depletion transistor and to the second data node. The depletion transistor is connected to the word line and to the second power supply point.

Method and apparatus for improving SRAM write operations

A memory cell includes an access transistor, first and second pull-up transistors, first and second pull-down transistors, and a first search transistor. The access transistor is connected to a first word line and connected between a first bit line and a first data node. The first pull-up transistor is connected to a first power supply point and the first data node, and the second pull-up transistor is connected to the first power supply point and the second data node. The first pull-down transistor is connected to a second power supply point and the first data node, and the second pull-down transistor is connected to the second power supply point and the second data node. The first search transistor is connected to the second data node and includes a source terminal connected to a third power supply point comprising a voltage less than the voltage at the second power supply point.

A memory device including a static random access memory (SRAM) cell comprising junction field effect transistors (JFETs) has been disclosed. The memory cell includes a first bipolar junction transistor (BJT) for driving a bit line at logic levels having a potential outside the potential range in which the SRAM cell operates. An amplifier including a level translator circuit provides a level shifting operation on the data provided by the bit line to provide level shifted data having a voltage swing within the potential range in which the SRAM cell operates. The level translator circuit includes a second BJT. In this way, fast read operation of a SRAM cell comprising JFETs may be provided.

Memory cell including an emitter follower and emitter follower sensing scheme and method of reading data therefrom

A level shifting circuit can include a first input junction field effect transistor (JFET) having a gate coupled to receive an input signal having a first voltage swing that provides a controllable impedance path between a first supply node and a first terminal of a first bias stack including at least one JFET. A driver circuit can be coupled to receive an output from the first bias stack that provides a level shifted output having a second voltage swing that is less than the first voltage swing.

Junction field effect transistor input buffer level shifting circuit

A level shifting circuit can include a first driver junction field effect transistor (JFET) having a source coupled to a reference supply node and a second driver JFET of a second conductivity type having a source coupled to a boosted supply node, and a first charge pump circuit. The first charge pump circuit can be coupled between the first driver control node and an input node coupled to receive an input signal, and can couple a first terminal of a first capacitor between a reference supply node and a power supply node in response to an input signal. The power supply node can be coupled to receive a power supply potential, the reference supply node can be coupled to receive a reference potential, and the boosted power supply node can be coupled to receive a boosted potential. The reference potential can be between the power supply potential and the boosted potential.

Level shifting circuit having junction field effect transistors

A range matching circuit () may include a range compare circuit () that receives a first range value from a first value store () and a second range value from a second range store (). A range compare circuit () can determine if a comparand value falls within a range defined by a first and second range value. A comparand value may also be applied to a compare section (). A compare section () can output an active a match result when a comparand value matches at least one entry in the compare section ().

Range compare circuit for search engine

A content addressable memory (CAM) () is disclosed that includes a value match mode, where a comparand value can be compared to a masked data value, and a range match mode where a comparand value can be compared to an upper range limit UR and a lower range limit LR. The CAM () may include a number of CAM cells (-to-) that may each be connected to a compare section (). A compare section () can include a first compare circuit () that may generate a match indication on a match line () and a second compare circuits (-to-). A more significant second compare circuits (-) may provide upper and lower limit match results (UMn, LMn) to a less significant first compare circuit ().

Content addressable memory (CAM) device with entries having ternary match and range compare functions

A sense amplifier, system and methods for increasing a noise margin of the sense amplifier are contemplated herein. In general, the sense amplifier includes a pair of cascode transistors coupled in parallel between a power supply node and a sense line of the sense amplifier. The sense amplifier also includes a precharge node coupled to the power supply node through a first precharge transistor, and a sense node coupled to the power supply node through a second precharge transistor. The sense amplifier described herein functions to separate the sense node from the precharge node with the pair of cascode transistors, which in turn, increases the noise margin of the sense amplifier by decoupling the sense node from any voltage fluctuations that may be present on the sense line during a sensing state.

Sense amplifier with dual cascode transistors and improved noise margin

A priority encoder circuit () for a content addressable memory (CAM) device is disclosed that may include a priority selection circuit () that receives match results (Mto Mz) and provides prioritized match results (Pto Pz), and a logic section () that logically combines prioritized match results (Pto Pz) to generate a smaller number of encoder inputs (RWLto RWLr). A logic section () can also generate a first portion (ID) of an encoded value (IDto IDX). Encoder entries (-to-) may each generate a second portion (IDto IDX) of an encoded value (IDto IDX).

Priority encoder circuit for content addressable memory (CAM) device

In a single ended simplex dual port memory cell, one port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.

Single ended simplex dual port memory cell

An apparatus comprising an oscillator circuit and a logic circuit. The oscillator circuit may be configured to present an output signal having a frequency in response to (i) a reference signal, (ii) a control signal and (iii) the output signal. The logic circuit may be configured to present the control signal in response to (i) the output signal and (ii) the reference signal. In one example, the logic circuit may disable the oscillator when the output signal oscillates outside a predetermined range.

Method, architecture and circuit for controlling and/or operating an oscillator

A single ended simplex dual port memory cell is described. One port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.

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Palo Alto, CA, United States of America

Richard K Chou