International Business Machines Corporation

Richard Joseph Branciforte

Gregory William Alexander

Deanna Postles Dunn Berger

Timothy Carl Bronson

Aaron Tsai

Christian Jacobi

Markus Kaltenbach

Ashraf ElSharif

Taylor J Pritchard

Michael F Fee

Robert J Sonnelitter, Iii

Michael Andrew Blake

Craig Raymond Walters

Jonathan T Hsieh

Edward Thomas Malley

Hieu Trong Huynh

Deanna P Berger

Jason D Kohl

Guy G Tracy

Deanna P D Berger

Avraham Ayzenfeld

Ram Sai Manoj Bamdhamravuri

Avery Francois

Lior Binyamini

Gregory Miaskovsky

Robert Sonnelitter

A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.

Shadow pointer directory in an inclusive hierarchical cache

To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.

Cache management using cache scope designation

A method and a computer system for core recovery management are provided. A first operation signal is generated via a first hardware agent. The first operation signal indicates that the first hardware agent is processing an operation requested by a first processor core. The first processor core receives a first extend fence signal based on the generated first operation signal. As long as the first extend fence signal is received via the first processor core, the first processor core is kept in a fenced state for core recovery.

Preventing extraneous messages when exiting core recovery

Embodiments are for special tracking pool enhancement for core L1 address invalidates. An invalidate request is designated to fill an entry in a queue in a local cache of a processor core, the queue including a first allocation associated with processing any type of invalidate request and a second allocation associated with processing an invalidate request not requiring a response in order for a controller to be made available, the entry being in the second allocation. Responsive to designating the invalidate request to fill the entry in the queue in the local cache, a state of the controller that made the invalidate request is changed to available based at least in part on the entry being in the second allocation.

Special tracking pool enhancement for core local cache address invalidates

Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

Lateral persistence directory states

Methods and systems for controlling writing to register files in a processing system having at least two execution pipelines are provided. Aspects include obtaining a micro operation for execution by an execution unit of a first pipeline in the processing system, wherein the micro operation includes writing data to a register file. Aspects also include determining whether the data will be accessed by an execution unit of a second pipeline in the processing system. Based on a determination that the data will only be accessed by the execution unit of the first pipeline, aspects include blocking writing of the data to a register file of the second pipeline.

Write power optimization for hardware employing pipe-based duplicate register files

A method includes allocating a first entry in a global completion table (GCT) on a processor, responsive to a first instruction group being dispatched, where the first entry corresponds to the first instruction group. A data value applicable to the first instruction group is identified. An offset value applicable to the first instruction group is calculated by subtracting, from the data value, a base value previously written to a second entry of the GCT for a second instruction group. The offset value is written in the first entry of the GCT in lieu of the data value.

Offset-based mechanism for storage in global completion tables

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Austin, TX, United States of America

Richard Joseph Branciforte