International Business Machines Corporation

Eastman-kodak Company

Omnivision Technologies, Inc.

Richard John Rassel

Jeffrey P Gambino

Mark David Jaffe

James William Adkisson

Robert K Leidy

John J Ellis-Monaghan

Edmund Juris Sprogis

Robert Mark Rassel

Kevin N Ogg

Stephen Ellinwood Luce

Zhong-Xiang He

Douglas Duane Coolbaugh

Anthony K Stamper

Rajendran Krishnasamy

Ebenezer E Eshun

Daniel Nelson Maynard

Timothy G Dunham

Charles S Musante

Edward T Nelson

Jeanne-Tania Sucharitaves

Qizhi Liu

Jeffrey Bowman Johnson

Alain F Loiseau

Robert Michael Guidash

R Michael Guidash

Charles V Stancampiano

Solomon Mulugeta

Valarmathi C Shanmugam

Jerome Brett Lasky

Paul Francis Fortier

Stephen Arthur St Onge

Charles F Musante

Anthony J Perri

Tian Xia

Stephen A Mongeon

Walter Victor Lepuschenko

Kristin M Ackerson

Sambasivan Narayan

Jeffery Peter Gambino

Brett Cucci

David Alan Meatyard

Alan Loiseau

The disclosure relates to semiconductor structures and, more particularly, to structures for preventing dicing damage on photonics wafers. The structure includes: an optical waveguide structure to optical fiber interface formed on an integrated circuit; and a groove formed in a substrate and which includes a structure preventing a fluid pressure of a dicing operation from damaging the substrate along the groove.

Structures for preventing dicing damage

Disclosed herein an image sensor chip, including a substrate having at least one via extending through at least one inter layer dielectric (ILD); a first conductive layer over the ILD, wherein the first conductive layer has a first thickness; a second conductive layer over the first conductive layer, wherein the second conductive layer has a second thickness of less than the first thickness; a polymer layer over the second conductive layer, the polymer layer including a cavity; a plurality of cavity components in the cavity; and protective layer contacting the polymer layer and covering the cavity.

Thick bond pad for chip with cavity package

CMOS pixel sensors with multiple pixel sizes and methods of manufacturing the CMOS pixel sensors with implant dose control are provided. The method includes forming a plurality of pixel sensors in a same substrate and forming a masking pattern over at least one of the plurality of pixel sensors that has a pixel size larger than a non-masked pixel sensor of the plurality of pixel sensors. The method further includes providing a single dosage implant to the plurality of pixel sensors. The at least one of the plurality of pixel sensors with the masking pattern receives a lower dosage than the non-masked pixel sensor.

Pixel sensors of multiple pixel size and methods of implant dose control

A method of preventing blooming in a pixel array includes affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element.

Anti-blooming pixel sensor cell with active neutral density filter, methods of manufacture, and design structure

CMOS pixel sensor cells with spacer transfer gates and methods of manufacture are provided herein. The method includes forming a middle gate structure on a gate dielectric. The method further includes forming insulation sidewalls on the middle gate structure. The method further includes forming spacer transfer gates on the gate dielectric on opposing sides of the middle gate, adjacent to the insulation sidewalls which isolate the middle gate structure from the spacer transfer gates. The method further includes forming a photo-diode region in electrical contact with one of the spacer transfer gates and a floating diffusion in electrical contact with another of the spacer transfer gates.

CMOS pixel sensor cells with poly spacer transfer gates and methods of manufacture

A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.

Interlevel conductive light shield

A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.

Methods of forming silicide strapping in imager transfer gate device

Pixel sensor cells, method of fabricating pixel sensor cells and design structure for pixel sensor cells. The pixel sensor cells including: a photodiode body in a first region of a semiconductor layer; a floating diffusion node in a second region of the semiconductor layer, a third region of the semiconductor layer between and abutting the first and second regions; and dielectric isolation in the semiconductor layer, the dielectric isolation surrounding the first, second and third regions, the dielectric isolation abutting the first, second and third regions and the photodiode body, the dielectric isolation not abutting the floating diffusion node, portions of the second region intervening between the dielectric isolation and the floating diffusion node.

Structures, design structures and methods of fabricating global shutter pixel sensor cells

Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.

IC chip and design structure including stitched circuitry region boundary identification

A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.

High surface area aluminum bond pad for through-wafer connections to an electronic package

Stitched circuitry region boundary identification for stitched IC chip layout

A method of forming a small geometry feature. The method includes forming a source layer on a top surface of a substrate; forming a mandrel on a top surface of the source layer, the mandrel having a sidewall; sputtering material from the source layer onto the sidewall of the mandrel to form a sidewall layer on the sidewall of the mandrel; and removing the mandrel. Also methods to forming wires and field effect transistors of integrated circuits.

Method of making small geometry features

A pixel sensor cell, a method for fabricating or operating the pixel sensor cell and a design structure for fabricating the pixel sensor cell each include a semiconductor substrate that includes a photoactive region separated from a floating diffusion region by a channel region. At least one gate dielectric is located upon the semiconductor substrate at least in-part interposed between the photoactive region and the floating diffusion region, and at least one optically transparent gate is located upon the gate dielectric and at least in-part over the channel region. Preferably, the at least one gate dielectric is also located over the photoactive region and the at least one optically transparent gate is also located at least in-part over the photoactive region, to provide enhanced charge transfer capabilities within the pixel sensor cell, which is typically a CMOS pixel sensor cell.

Pixel sensor cell, methods and design structure including optically transparent gate

A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

Image sensor monitor structure in scribe area

Growing community of inventors

Colchester, VT, United States of America

Richard John Rassel