Cadence Design Systems, Inc.

Richard John O'Donovan

Donald John O'Riordan

John Yanjiang Shu

Hongzhou Liu

Wangyang Zhang

Wei Michael Tian

Michael Tian

Walter E Hartong

Saibal Saha

Prabal Kanti Bhattacharya

Jushan Xie

Jaideep Mukherjee

Monica Goel

Claudia Ursula Roesch

Embodiments include herein are directed towards a method for electromigration analysis of a circuit design. Embodiments may include performing a first transient simulation of an electronic design using one or more electronic design tools. Embodiments may further include storing a level of current associated with one or more generic passive device tap points. Embodiments may also include identifying a resistor capacitor (RC) model for one or more generic passive devices using the one or more electronic design tools and performing a second transient simulation for the one or more generic passive devices. Embodiments may further include analyzing a current density obtained from the first and second transient simulation to obtain a single current density map.

System and method for dual model electromagnetic modeling in an electronic circuit design

A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.

Sampling selection for enhanced high yield estimation in circuit designs

Various embodiments implement an electronic design with one or more electrical analyses or simulations. Pre-layout and/or post-layout design data of an electronic design or a portion thereof may be identified at a physical design implementation module. A first stage analysis may be performed on the electronic design or the portion thereof at least by computing electrical characteristics with a reduced representation in the electronic design or the portion thereof. Electrical behavior of the electronic design or the portion thereof may be generated at least by performing a second stage analysis on the electronic design or the portion thereof with one or more adjusted electrical characteristics. The electronic design or the portion thereof may then be implemented based in part or in whole upon the one or more electrical analyses or simulations.

Methods, systems, and computer program products for implementing an electronic design using voltage-based electrical analyses and simulations with corrections

A system, method, and computer program product for facilitating model binning in circuit simulators. Embodiments enable specification of models spanning binning dimensions, such as device width and length, in a model group via inheritable model bins. New simulator modeling syntax and semantics eliminate much of the redundancy and parsing overhead from model parameter specifications in foundry process design kits. Indirect and optional inheritance is also enabled, allowing for fine grain and coarse grain grids in the same model group.

Spice model bin inheritance mechanism

Various embodiments implement an electronic design with power gate analyses using time varying resistors. Design data of an electronic design or a portion thereof may be identified at an electronic design implementation module. First stage electrical characteristics may be generated at least by performing a first stage electrical analysis on a reduced representation of the electronic design or the portion thereof. Second stage electrical characteristics may further be generated at least by performing a second stage electrical analysis on a parasitic injected representation of the electronic design or the portion thereof with a time-varying model for the power gate. The electronic design or the portion thereof may then be further implemented based in part or in whole upon the one or more electrical analyses or simulations.

Methods, systems, and computer program products for implementing an electronic design with time varying resistors in power gating analysis

A system, method, and computer program product for improving circuit reliability via circuit schematic simulation. A circuit simulator may netlist and simulate a schematic with a reference stimulus and determine whether a circuit component is a candidate for stress analysis, and store candidate component circuit conditions. A stress test simulation may determine if candidate components are stressed by exposure to simulated conditions meeting a stress test criterion, and output information regarding stressed circuit components. Embodiments may simulate analog integrated circuitry, determine MOS component gate oxide layer area according to component length and width, and monitor conditions on components deemed most likely to be defective, including larger MOS components. A circuit simulator plug-in may avoid storing simulation output waveforms or performing layout based analysis. Embodiments may modify the netlist and/or the test stimulus to increase the percentage of stressed circuit components, including bypassing voltage regulators and adding test connections.

Simulation based system and method for gate oxide reliability enhancement

A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units ('vunits'), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits reference a top-level circuit or subcircuits (by name or by specific instance), and the simulator automatically binds vunit contents appropriately during circuit hierarchy expansion. Vunits may be re-used for other design cells, and may be easily processed by text-based design tools. Vunits may be provided via vunit_include statements in a control netlist file, command line arguments, or by directly placing a vunit block into a netlist. Vunits may also contain instance statements to monitor or process signals, such as those needed by assertions.

System and method for containing analog verification IP

A netlist description that includes embedded code segments for describing a circuit is preprocessed in order to replace the embedded code segments with corresponding preprocessed code segments, where the preprocessed code segments include netlist code that can be parsed and executed. To perform this preprocessing, programming languages that include scripting operations are identified for the embedded code segments in the netlist description. A pipeline preprocessor that includes preprocessors for the identified programming languages is configured to sequentially process the netlist description and replace the embedded code segments with the corresponding preprocessed code segments.

Chained programming language preprocessors for circuit simulation

Systems and methods for simulating and verifying a design are contemplated. Various embodiments determine a set of verification rules for a design, wherein the verification rules use a PSL or SVA syntax in a SPICE netlist to describ a property of the circuit design. The state of a circuit at a simulated first time, t, can be determined. The state at the first time, t, may be analyzed to determine if a triggering event has occurred. Based on the occurrence of the triggering event, the systems and methods can verify the state at the first time, t, against the set of verification rules. Some embodiments of the systems and methods described herein can include a mixed-signal circuit including an analog portion and a digital portion, and the analog portion, the mixed-signal portion, or both, may be simulated and verified.

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San Jose, CA, United States of America

Richard John O'Donovan