European Space Agency

Richard Jansen

Scott Lindner

Boris Glass

Gianluca Furano

Jorgen Ilstad

A bi-state driver circuit for switching an output terminal between a first predetermined voltage level and a high impedance state, which involves a first string of transistors connected between the output terminal and the first predetermined voltage level at least a first transistor arranged closer to the first predetermined voltage level, a second transistor arranged closer to the output terminal, a voltage divider circuit connected between the output terminal and a voltage level of a control signal attaining voltage levels between the first predetermined voltage level and a second predetermined voltage level, including at least one intermediate node having an intermediate voltage level between a voltage level of the output terminal and the voltage level of the control signal, and a second string of transistors connected between the intermediate node of the voltage divider circuit and the second predetermined voltage level, and including at least a third transistor.

High voltage tolerant CMOS driver for low-voltage bi-directional communication buses

A transceiver for imparting a voltage signal on a differential signaling bus, involving an output terminal and a string of one or more transistors connected between the output terminal and a predetermined voltage level. The transceiver can be switched between an active state in which the predetermined voltage level is applied to the output terminal, and an inactive state in which the predetermined voltage level is not applied to the output terminal. Methods for the transceiver can involve a detection step of detecting a first quantity depending on a current flowing through a first transistor in the string of transistors, a failure determination step of determining whether the detected first quantity satisfies one or more error conditions, and a control step of switching the transceiver to the inactive state if the detected first quantity is determined to satisfy at least one of the one or more error conditions.

Bus failure detection transceiver architecture and transceiver operation method

A method of determining link failure in a receiver for receiving a differential voltage signal via a first signal line and a second signal line, the method including: obtaining a first quantity depending on the larger one of a maximum value over time of a voltage level that is attained in the first signal line and a maximum value over time of a voltage level that is attained in the second signal line; obtaining a second quantity depending on a maximum value over time of an average of an instantaneous voltage level in the first signal line and an instantaneous voltage level in the second signal line; and determining that the link failure has occurred on the basis of the first quantity and the second quantity.

Growing community of inventors

Oegstgeest, Netherlands

Richard Jansen