Linear Technology Corporation

International Business Machines Corporation

Analog Devices International Unlimited Company

Richard James Reay

David M Thomas

Klaas Berend Klaassen

Richard T Owen

Eric C Welde

Derek Redmayne

Techniques for improving a power supply accuracy of a precision data converter system, such as analog-to-digital converter circuits (ADCs) and digital-to-analog converter circuits (DACs). Improving the power supply accuracy can enable a reference voltage to be as large as possible, thereby increasing the signal-to-noise-ratio (SNR). The techniques can also simplify power supply sequencing requirements for the data converter system.

Data converter system with improved power supply accuracy and sequencing

A current source is switchable between two precisely defined output currents. A terminal of a coupling capacitor is coupled to the gate of an output MOSFET. The other terminal of the capacitor is switched between two reference voltages to toggle the output MOSFET to output the selected one of the two currents. A switchable bias voltage source is coupled to the gate only during the on state of the output MOSFET to set the gate voltage of the output MOSFET. The current output of the current source is quickly and accurately changed. A reference MOSFET is not directly coupled to the output MOSFET, so there are no slow settling components coupled to the gate of the output MOSFET.

Capacitively coupled switched current source

A method and system for converting a digital code. A digital signal is encoded to have a digital code having multiple binary bits. Substantially one half of the binary bits of the digital code is inverted to produce a modified digital code to reduce digital noise associated with the digital code.

Method and system for bit polarization coding

A method and system is provided for clock input mode selection. When a signal provided on one of two clock input terminals is received, the received signal is considered in connection with a second input signal in order to determine whether the first input signal and the second input signal satisfy a pre-determined condition. Based on whether the pre-determined condition is met, a clock input mode is selected that indicates whether the clock input terminals provide a differential clock input or a single-ended digital clock input.

Method and system for determining a clock input mode

Circuits and methods are provided that compensate for dynamic errors caused by voltage drops across a switch coupled in series with a capacitor in an electrical circuit such as a track-and-hold circuit. In such circuits, the capacitor should provide the same voltage as a signal coupled to the switch, but does not because of the switch voltage drop. The switch can be, for example, a MOSFET or more particularly a CMOS device. Dynamic errors are compensated for by measuring the voltage drop across the switch and then effectively adding the measured voltage drop to a voltage provided by the capacitor.

Dynamic error compensation in track-and-hold circuits

Improved pipelined successive approximation analog-to-digital converter circuits are provided. Some embodiments of the present invention comprises two stages in which a first portion of the total bits are evaluated in the first stage of the circuit and then the residue is passed to the second stage of the circuit that evaluates the remaining portion. By operating both stages simultaneously, the throughput is increased. These embodiments utilize two matched buffers to isolate the first and second stages from switching errors of a sampling circuit and the loading effects of comparators associated with the two stages. In another embodiment, upon completion of the conversion of the MSBs, the remaining input signal or residue signal is amplified by a preamp and the output is subsequently sampled by a residue sample and hold circuit (S/H). After the residue is sampled by the residue S/H, the second stage begins to solve the least significant bits (LSBs). The second stage is a matched copy of the first stage. Furthermore, if the CDACs and the preamps corresponding to the two stages are matched, the actual value of the preamp gain does not affect converter linearity. In yet another embodiment, a single preamp buffer is switched between the first and second stages. The preamp provides buffering of the top plates of the capacitor array from the residue sampling switch.

Pipelined successive approximation analog-to-digital converters

Thermal transient signal detection/correction circuitry corrects for errors caused by actual thermal asperities and baseline wander in the analog signal from a magnetoresistive (MR) sensor, such as an MR read head in a magnetic recording disk drive. In a disk drive with an MR head the detection/correction circuitry is located between the MR head signal amplifier and the data readback channel so that the thermal transients are corrected in the analog data signal prior to processing of the analog data signal into digital data. A detection circuit receives the analog data signal from the MR head, low-pass filters the signal and generates a thermal asperity event signal if the filtered signal exceeds a predetermined threshold. A correction circuit also receives the analog data signal from the MR head and includes a high-pass filter whose pole frequency is controlled by the thermal asperity event signal from the detection circuit. In the event of a detected thermal transient the pole frequency is quickly raised to bring the baseline of the analog data signal back to normal, which turns off the output of the detection circuit. The correction circuit then lowers the pole frequency gradually. The thermal transient detection/correction circuit thus quickly restores the baseline of the analog data signal to zero, quickly enables data to be read after the onset of a thermal transient and eliminates undershoot in the analog data signal due to the slowly changing tail of the thermal transient.

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Mountain View, CA, United States of America

Richard James Reay