Semtech Corporation

Richard James Lansdowne

Jonathan Lamb

Wolfgang Bruchner

A system and method of synchronizing clocks in a distributed network is disclosed. A simple 1-pulse-per-second timing pulse is routed to time-stamping units in each network device and utilized to measure traffic-dependent synchronization packet residence delays within network elements. Synchronization messages are updated to reflect the measured residence times, thus creating transparent clocks that can readily be synchronized across the network. The simple timing pulse architecture allows the method to be applied readily both to new designs and to retrofit existing hardware.

Measurement and adjustment of real-time values according to residence time in networking equipment without access to real time

A phase detector and signal locking system controller for use in a digital phase-locked loop (PLL) application includes a first and a second phase detector where the first phase detector result is used to control the initial pull-in and the second phase detector is used to control fine tuning once the phase differences are too small for appropriate detection by the first phase detector. A post processing and control unit operates to effectively merge the two phase detector outputs and to apply the appropriate gain factor that can be used to control a PLL system.

Phase detector and signal locking system controller

A clock synthesizer produces an output clock that has a programmable phase offset from the input clock. The clock synthesizer includes an accumulator and an offset adder. The output clock is derived from the offset adder. The offset adder receives a value derived from the accumulator and a selected phase offset value. The phase difference between the non-aligned output clock and the aligned output clock is determined by the phase offset value. The time resolution of the clock synthesizer may be defined by the clock rate of the system and the number of bits used in the offset adder and the accumulator.

Method and apparatus for controlling the phase of the clock output of a digital clock

An asynchronous timing oscillator re-synchronizer enables a clocked system which uses a high frequency clock to measure time intervals to re-synchronize to the clock after it has been temporarily disabled, using a low frequency, low accuracy, low power clock to determine the number of high frequency clock cycles that would have occurred during such intervals. Both high frequency and low frequency clocks are provided to the re-synchronizer, and the ratio between their respective frequencies is periodically determined and stored. A command sent to the re-synchronizer disables the high frequency clock for a specified number of cycles of the low frequency clock. When the disablement period has expired, the high frequency clock is re-enabled. While the high frequency clock is disabled, a register is periodically incremented by the stored clock ratio, such that when the high frequency clock is re-enabled, the number in the register represents the number of high frequency clock cycles that would have occurred during the disablement period. This number is provided to the clocked system to re-synchronize the clocked system to the high frequency clock.

Asynchronous timing oscillator re-synchronizer and method

A clock output controller using a digital frequency synthesis minimizes the clock output disturbance due to input reference signal switchover. The controller includes a first and a second accumulator where the Most Significant Bit (MSB) of the first accumulator output generates the clock output signal and the MSB of the second accumulator generates a feedback signal. A reset control signal is generated by the transition edge detector/switchover controller and it is coupled to the register block of the second accumulator in order to reset the feedback signal at an appropriate time so as to match the phase of the new reference signal. A hold control signal is also generated to keep the clock output locked on the old reference signal until the feedback signal is locked to the new signal. The hold signal is then reset once locking to the new reference signal is accomplished and the clock output is fully switched over with minimal disturbance.

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Romsey, United Kingdom

Richard James Lansdowne